From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16666 invoked by alias); 29 Nov 2013 09:41:57 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 16655 invoked by uid 89); 29 Nov 2013 09:41:56 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.2 required=5.0 tests=AWL,BAYES_50,RDNS_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no version=3.3.2 X-HELO: mga11.intel.com Received: from Unknown (HELO mga11.intel.com) (192.55.52.93) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 29 Nov 2013 09:41:55 +0000 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 29 Nov 2013 01:41:47 -0800 X-ExtLoop1: 1 Received: from irsmsx103.ger.corp.intel.com ([163.33.3.157]) by fmsmga002.fm.intel.com with ESMTP; 29 Nov 2013 01:41:40 -0800 Received: from irsmsx104.ger.corp.intel.com ([169.254.5.135]) by IRSMSX103.ger.corp.intel.com ([169.254.3.66]) with mapi id 14.03.0123.003; Fri, 29 Nov 2013 09:41:39 +0000 From: "Tedeschi, Walfred" To: Eli Zaretskii CC: "palves@redhat.com" , "gdb-patches@sourceware.org" Subject: RE: [PATCH v2 1/1] Documentation for MPX. Date: Fri, 29 Nov 2013 12:07:00 -0000 Message-ID: References: <1385636042-10592-1-git-send-email-walfred.tedeschi@intel.com> <83mwko8ev7.fsf@gnu.org> In-Reply-To: <83mwko8ev7.fsf@gnu.org> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2013-11/txt/msg00899.txt.bz2 Hi Eli, Thanks for your review!=20 About the "Architecture": You have made a comment on another place about Ra= w values/Architecture values. That was changed. The line is this one: +This way the raw value can be accessed via bnd0raw@dots{}bnd3raw. An= y=20 +change on bnd0@dots{}bnd3 or bnd0raw@dots{}bnd3raw is reflect on its= =20 +counterpart. Before: +This way the architecture value can be accessed via bnd0raw...bnd3raw.= =20=20=20 +Any change on bnd0..bnd3 or bnd0raw...bnd3raw is reflect on its=20 +counterpart. When displaying I will add here a list of changes in V2: 1. Added @cindex for MPX and @def for MPX. 2.Exchanged "..." by @dots{} 3.Fix typo on "Architecture registers...." as mentioned. 4.Example is fixed (using "@{" for "{" and "@}" for "}"). About the phrase: >+Architecture registers @samp{BND0} through @samp{BND3} are=20 > +represented in @value{GDBN} as @samp{bnd0raw} through @samp{bnd3raw}.=20 My intention was to emphasize that the BND register, as presented on Intel = manual, is represented in GDB by bndraw. Therefore the use of " Architectu= re registers". Since we have already defined that BND are the architecture register we cou= ld omit the "Architecture Registers on the phrase writing like: >+@samp{BND0} through @samp{BND3} are=20 > +represented in @value{GDBN} as @samp{bnd0raw} through @samp{bnd3raw}. What do you think? Thanks a lot and best regards, -Fred=20 -----Original Message----- From: Eli Zaretskii [mailto:eliz@gnu.org]=20 Sent: Thursday, November 28, 2013 9:13 PM To: Tedeschi, Walfred Cc: palves@redhat.com; gdb-patches@sourceware.org Subject: Re: [PATCH v2 1/1] Documentation for MPX. > From: Walfred Tedeschi > Cc: gdb-patches@sourceware.org, Walfred Tedeschi=20 > > Date: Thu, 28 Nov 2013 11:54:02 +0100 >=20 > I tried to cover all feedback you gave me. > Concerning the footnote I have reduced it to avoid early confusion,=20 > the topic will be explained anyhow later. Thanks. > diff --git a/gdb/NEWS b/gdb/NEWS > index 9fc3638..fdb33d4 100644 > --- a/gdb/NEWS > +++ b/gdb/NEWS > @@ -5558,3 +5558,5 @@ GDB now handles cross debugging. If you are=20 > remotely debugging between two different machines, type ``./configure ho= st -target=3Dtarg''. > Host is the machine where GDB will run; targ is the machine where=20 > the program that you are debugging will run. > + > + * GDB now supports access to Intel(R) MPX registers on GNU/Linux. This is OK. > +@cindex Intel(R) Memory Protection Extensions (MPX). > +@subsubsection Intel(R) @dfn{Memory Protection Extensions} (MPX). @cindex should be after the @subsubsection line. > +@item bnd0raw..bnd3raw and bnd0@dots{}bnd3 registers display. > +Memory Protection Extension (MPX) adds the bound registers=20 > +@samp{BND0} @footnote{The register named with capital letters=20 > +represent the architecture registers.} through @samp{BND3}. Bound=20 > +registers store a pair of 64-bit values which are the lower bound and=20 > +upper bound. Bounds are effective addresses or memory locations.=20=20 > +The upper bounds are architecturally represented in 1's complement=20 > +form. A bound having lower bound =3D 0, and upper bound =3D 0 (1's comp= lement of all bits set) will allow access to the entire address space. > + > +Architecture registers @samp{BND0} through @samp{BND3} are=20 > +represented in @value{GDBN} as @samp{bnd0raw} through @samp{bnd3raw}. Hmm... didn't I suggest to use "raw registers" instead of "architectural re= gisters"? In fact, what are the differences between this version of the pa= tch and the previous one, they seem identical. Intel GmbH Dornacher Strasse 1 85622 Feldkirchen/Muenchen, Deutschland Sitz der Gesellschaft: Feldkirchen bei Muenchen Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk Registergericht: Muenchen HRB 47456 Ust.-IdNr./VAT Registration No.: DE129385895 Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052