From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15558 invoked by alias); 20 Nov 2013 13:08:05 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 15547 invoked by uid 89); 20 Nov 2013 13:08:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.1 required=5.0 tests=AWL,BAYES_50,RDNS_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no version=3.3.2 X-HELO: mga14.intel.com Received: from Unknown (HELO mga14.intel.com) (143.182.124.37) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 20 Nov 2013 13:08:03 +0000 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by azsmga102.ch.intel.com with ESMTP; 20 Nov 2013 05:07:54 -0800 X-ExtLoop1: 1 Received: from irsmsx102.ger.corp.intel.com ([163.33.3.155]) by fmsmga001.fm.intel.com with ESMTP; 20 Nov 2013 05:07:53 -0800 Received: from irsmsx152.ger.corp.intel.com (163.33.192.66) by IRSMSX102.ger.corp.intel.com (163.33.3.155) with Microsoft SMTP Server (TLS) id 14.3.123.3; Wed, 20 Nov 2013 13:07:52 +0000 Received: from irsmsx104.ger.corp.intel.com ([169.254.5.135]) by IRSMSX152.ger.corp.intel.com ([169.254.6.169]) with mapi id 14.03.0123.003; Wed, 20 Nov 2013 13:07:52 +0000 From: "Tedeschi, Walfred" To: "Tedeschi, Walfred" , "Mark Kettenis (mark.kettenis@xs4all.nl)" , "gdb-patches@sourceware.org" Subject: [pushed] [PATCH V7 0/8] Intel(R) MPX register support Date: Wed, 20 Nov 2013 13:11:00 -0000 Message-ID: Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2013-11/txt/msg00594.txt.bz2 Hello All, I have just pushed this patch series, excluding doc, and x32 support (where= as MPX does not apply) as mentioned in: https://sourceware.org/ml/gdb-patches/2013-11/msg00284.html Doc patch will be send ad-hoc. Thanks a lot Pedro, Mark and Eli for the reviews! Regards, -Fred -----Original Message----- From: gdb-patches-owner@sourceware.org [mailto:gdb-patches-owner@sourceware= .org] On Behalf Of Tedeschi, Walfred Sent: Thursday, October 17, 2013 2:00 PM To: Mark Kettenis (mark.kettenis@xs4all.nl); gdb-patches@sourceware.org Subject: [ping] [PATCH V7 0/8] Intel(R) MPX register support Mark and all, =46rom my side I prepared a version removing the x32 MPX support.=20 Another small fix was also introduced: (i386_validate_tdesc_p) where a comparison should be "< 0" and not "=3D=3D= 0" By the way we also have almost ready for review AVX512 that will be on top = of MPX. Thanks and regards, -Fred -----Original Message----- From: Tedeschi, Walfred Sent: Wednesday, October 09, 2013 2:00 PM To: tromey@redhat.com; mark.kettenis@xs4all.nl Cc: gdb-patches@sourceware.org; Tedeschi, Walfred Subject: [PATCH V7 0/8] Intel(R) MPX register support Mark and all, I have noticed no feedback on this patch series.=20 Is there a major change that you would like to see in here? Thanks a lot for your support, Best regards, -Fred This patch series adds support for the Intel(R) Memory Protection Extension= MPX registers. Native and remote debugging are covered by this patch. New registers are bound registers known as bnd register (bnd0...bnd3), a co= nfiguration register bndcfgu and a status register bndstatus. Bound regist= ers store pointer bounds, i.e. bound limits of a pointer. Bndstatus and bn= dcfgu store information of the current status and configuration of other MP= X counterparts. For more information [1][2]. Design notes: Bound register are represented in hardware as two fields of 64bits each, bo= th in 64bit and 32bit mode. The fields are lower bound and upper bound. Upper bound value is a complement of one value of the upper limiting addres= s. To take this into account the bnd0...bnd3 are created as pseudo register= s while the hardware values are stored on bnd0raw...bnd3raw. Ok to commit? References: [1] Intel(R) Architecture Instruction Set Extensions Programming Reference. http://download-software.intel.com/sites/default/files/319433-015.pdf. [2] http://software.intel.com/en-us/intel-isa-extensions.=20 Approvals: Documentation (8/8) was approved by Eli. Changes between V6 and V7: * Fixed initialization of MPX registers in i386_gdbarch_init.=20 This fixed some regressions. * Fixed indentation for macros on i386-xstate.h. * Preserved symmetry of initializing the I386_LINUX_ORIG_EAX_REGNUM using the way it was used formely by AVX. =09 Changes between V5 and V6: * Removed some fields from gdbarch_tdep and added them as macros, as indicated by Mark Kettenis. * Fixed a comparison for XCR0 on gdbserver implementation.=09 Changes between V4 and V5: * Improved text for MPX feature on gdb.texinfo following Eli indications. * Fixed one table that still had ORIG_EAX and ORIG_RAX in the middle. Changes between V3 and V4: * Added NEWS entry for MPX. * Improved text for MPX feature on gdb.texinfo. * Fixed several ChangeLogs. Changes between V2 and V3: * Small changes on changelogs: "Add MPX support for i386" and "Add=20 support for MPX amd64". * Add MPX feature documentation as extra patch. Changes between V1 and V2: * Folowing the Mark Kettenis feedback: Orig_rax and orig_eax are left as t= he last register on the internal list. * Ported gcc file used for cpuid and corrected overlooked condition to=20 detect MPX hardware while performing MPX related tests.=20 Walfred Tedeschi (8): Fix conditions in creating a bitfield. Add MPX registers XML files. Add MPX support for i386 MPX for amd64 Add MPX support to gdbserver. Add pretty-printer for MPX bnd registers. Add MPX registers tests. Add MPX feature description to GDB manual. gdb/NEWS | 2 + gdb/amd64-linux-nat.c | 43 ++++- gdb/amd64-linux-tdep.c | 14 +- gdb/amd64-linux-tdep.h | 4 +- gdb/amd64-tdep.c | 16 ++ gdb/amd64-tdep.h | 8 +- gdb/common/i386-gcc-cpuid.h | 8 +- gdb/common/i386-xstate.h | 20 ++- gdb/data-directory/Makefile.in | 1 + gdb/doc/gdb.texinfo | 25 +++ gdb/features/Makefile | 38 ++++- gdb/features/i386/32bit-mpx.xml | 43 +++++ gdb/features/i386/64bit-mpx.xml | 43 +++++ gdb/features/i386/amd64-mpx-linux.c | 211 +++++++++++++++++++++= +++ gdb/features/i386/amd64-mpx-linux.xml | 19 +++ gdb/features/i386/amd64-mpx.c | 206 +++++++++++++++++++++= ++ gdb/features/i386/amd64-mpx.xml | 17 ++ gdb/features/i386/i386-mpx-linux.c | 187 +++++++++++++++++++++ gdb/features/i386/i386-mpx-linux.xml | 19 +++ gdb/features/i386/i386-mpx.c | 182 ++++++++++++++++++++ gdb/features/i386/i386-mpx.xml | 17 ++ gdb/features/i386/x32-mpx-linux.c | 211 +++++++++++++++++++++= +++ gdb/features/i386/x32-mpx-linux.xml | 19 +++ gdb/features/i386/x32-mpx.c | 206 +++++++++++++++++++++= ++ gdb/features/i386/x32-mpx.xml | 17 ++ gdb/gdbserver/Makefile.in | 15 ++ gdb/gdbserver/configure.srv | 20 +-- gdb/gdbserver/i387-fp.c | 90 ++++++++++ gdb/gdbserver/linux-x86-low.c | 87 ++++++++-- gdb/i386-linux-nat.c | 17 +- gdb/i386-linux-tdep.c | 9 +- gdb/i386-linux-tdep.h | 4 +- gdb/i386-tdep.c | 219 +++++++++++++++++++++= +++- gdb/i386-tdep.h | 24 ++- gdb/i387-tdep.c | 130 ++++++++++++++- gdb/i387-tdep.h | 9 + gdb/python/lib/gdb/command/bound_registers.py | 45 +++++ gdb/regformats/i386/amd64-mpx-linux.dat | 84 ++++++++++ gdb/regformats/i386/amd64-mpx.dat | 83 ++++++++++ gdb/regformats/i386/i386-mpx-linux.dat | 60 +++++++ gdb/regformats/i386/i386-mpx.dat | 59 +++++++ gdb/regformats/i386/x32-mpx-linux.dat | 84 ++++++++++ gdb/regformats/i386/x32-mpx.dat | 83 ++++++++++ gdb/target-descriptions.c | 2 +- gdb/testsuite/gdb.arch/i386-mpx.c | 92 +++++++++++ gdb/testsuite/gdb.arch/i386-mpx.exp | 142 ++++++++++++++++ gdb/testsuite/gdb.python/py-pp-maint.exp | 8 +- gdb/testsuite/gdb.xml/maint_print_struct.xml | 1 + 48 files changed, 2871 insertions(+), 72 deletions(-) create mode 100644 = gdb/features/i386/32bit-mpx.xml create mode 100644 gdb/features/i386/64bit= -mpx.xml create mode 100644 gdb/features/i386/amd64-mpx-linux.c create mode 100644 gdb/features/i386/amd64-mpx-linux.xml create mode 100644 gdb/features/i386/amd64-mpx.c create mode 100644 gdb/f= eatures/i386/amd64-mpx.xml create mode 100644 gdb/features/i386/i386-mpx-l= inux.c create mode 100644 gdb/features/i386/i386-mpx-linux.xml create mode 100644 gdb/features/i386/i386-mpx.c create mode 100644 gdb/fe= atures/i386/i386-mpx.xml create mode 100644 gdb/features/i386/x32-mpx-linu= x.c create mode 100644 gdb/features/i386/x32-mpx-linux.xml create mode 100644 gdb/features/i386/x32-mpx.c create mode 100644 gdb/fea= tures/i386/x32-mpx.xml create mode 100644 gdb/python/lib/gdb/command/bound= _registers.py create mode 100644 gdb/regformats/i386/amd64-mpx-linux.dat create mode 100644 gdb/regformats/i386/amd64-mpx.dat create mode 100644 g= db/regformats/i386/i386-mpx-linux.dat create mode 100644 gdb/regformats/i386/i386-mpx.dat create mode 100644 gd= b/regformats/i386/x32-mpx-linux.dat create mode 100644 gdb/regformats/i386/x32-mpx.dat create mode 100644 gdb= /testsuite/gdb.arch/i386-mpx.c create mode 100644 gdb/testsuite/gdb.arch/i= 386-mpx.exp -- 1.7.10.4 Intel GmbH Dornacher Strasse 1 85622 Feldkirchen/Muenchen, Deutschland Sitz der Gesellschaft: Feldkirchen bei Muenchen Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk Registergericht: Muenchen HRB 47456 Ust.-IdNr./VAT Registration No.: DE129385895 Citibank Frankfurt a.M. (BLZ 5= 02 109 00) 600119052 Intel GmbH Dornacher Strasse 1 85622 Feldkirchen/Muenchen, Deutschland Sitz der Gesellschaft: Feldkirchen bei Muenchen Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk Registergericht: Muenchen HRB 47456 Ust.-IdNr./VAT Registration No.: DE129385895 Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052