From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 13887 invoked by alias); 11 Nov 2013 08:16:12 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 13876 invoked by uid 89); 11 Nov 2013 08:16:11 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.6 required=5.0 tests=AWL,BAYES_00,RDNS_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no version=3.3.2 X-HELO: mga14.intel.com Received: from Unknown (HELO mga14.intel.com) (143.182.124.37) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 11 Nov 2013 08:16:09 +0000 Received: from azsmga002.ch.intel.com ([10.2.17.35]) by azsmga102.ch.intel.com with ESMTP; 11 Nov 2013 00:15:41 -0800 X-ExtLoop1: 1 Received: from irsmsx104.ger.corp.intel.com ([163.33.3.159]) by AZSMGA002.ch.intel.com with ESMTP; 11 Nov 2013 00:15:40 -0800 Received: from irsmsx153.ger.corp.intel.com (163.33.192.75) by IRSMSX104.ger.corp.intel.com (163.33.3.159) with Microsoft SMTP Server (TLS) id 14.3.123.3; Mon, 11 Nov 2013 08:15:36 +0000 Received: from irsmsx104.ger.corp.intel.com ([169.254.5.89]) by IRSMSX153.ger.corp.intel.com ([169.254.9.103]) with mapi id 14.03.0123.003; Mon, 11 Nov 2013 08:15:36 +0000 From: "Tedeschi, Walfred" To: Mark Kettenis , "gdb-patches@sourceware.org" Subject: RE: [PATCH V7 0/8] Intel(R) MPX register support Date: Mon, 11 Nov 2013 08:24:00 -0000 Message-ID: References: <1381320034-4092-1-git-send-email-walfred.tedeschi@intel.com> <201310201923.r9KJN3O2018018@glazunov.sibelius.xs4all.nl> <201311041029.rA4ATxrR007449@glazunov.sibelius.xs4all.nl> In-Reply-To: <201311041029.rA4ATxrR007449@glazunov.sibelius.xs4all.nl> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2013-11/txt/msg00276.txt.bz2 Hello Mark, I am not sure I got it right. Is this a ok to commit? If so, I still would like to do some changes before proceeding. Basically I want to remove the x32 support since it makes no sense and a re= gression I caused. Those changes where mentioned here: https://sourceware.org/ml/gdb-patches/2013-10/msg00513.html To avoid sending you a full patch again my Idea is to send an ad-hoc patch = to be added on top of my V7.=20 While doing the commit then I would join then on the respective place. Thanks a lot for your support and best regards, -Fred -----Original Message----- From: Mark Kettenis [mailto:mark.kettenis@xs4all.nl]=20 Sent: Monday, November 04, 2013 11:30 AM To: Tedeschi, Walfred Cc: Tedeschi, Walfred; tromey@redhat.com; gdb-patches@sourceware.org Subject: Re: [PATCH V7 0/8] Intel(R) MPX register support > From: "Tedeschi, Walfred" > Date: Mon, 4 Nov 2013 09:06:06 +0000 >=20 > Mark, >=20 > Do you think the proposal makes sense?=20 Sorry. No I don't think that makes sense. So I think you should go ahead = and commit your diff as-is (i.e. with both bndN and bndNraw register names). Cheers, Mark > -----Original Message----- > From: gdb-patches-owner@sourceware.org=20 > [mailto:gdb-patches-owner@sourceware.org] On Behalf Of Tedeschi,=20 > Walfred > Sent: Monday, October 21, 2013 1:33 PM > To: Mark Kettenis > Cc: tromey@redhat.com; gdb-patches@sourceware.org > Subject: RE: [PATCH V7 0/8] Intel(R) MPX register support >=20 > Mark, >=20 > Our internal users of MPX found it useful to see the raw value, processed= values and size together. > They found out that it was really handy to avoid doing the complement of = one for every bound manipulation. > (I our first patch we changed the type system to add a complement of=20 > one type, but this was considered overkill) >=20 > In this sense we would like still to display the bounds on a friendly man= ner to the user. When I say friendly I mean displaying values that are mean= ingful to the user. > ->Lower and upper bound should be presented as address format.=20 > ->No additional manipulation needed to calculate the upper bound limit. >=20 > On the other hand we could add the nice display on the python script and = eliminate the pseudo register set, having only "bndN". >=20 > Would you be ok with such a change? > (Having the pretty print only on the python side and eliminating the=20 > bndraws) >=20 >=20 > Thanks and regards, > -Fred. >=20 > PS: You might use SDE to have an idea how it looks like. > http://software.intel.com/en-us/articles/using-intel-mpx-with-the-inte > l-software-development-emulator=20 > http://software.intel.com/en-us/articles/intel-software-development-em > ulator >=20 >=20 >=20 > -----Original Message----- > From: gdb-patches-owner@sourceware.org=20 > [mailto:gdb-patches-owner@sourceware.org] On Behalf Of Mark Kettenis > Sent: Sunday, October 20, 2013 9:23 PM > To: Tedeschi, Walfred > Cc: tromey@redhat.com; gdb-patches@sourceware.org; Tedeschi, Walfred > Subject: Re: [PATCH V7 0/8] Intel(R) MPX register support >=20 > > From: Walfred Tedeschi > > Cc: gdb-patches@sourceware.org, Walfred Tedeschi=20 > > > >=20 > > Mark and all, > >=20 > > I have noticed no feedback on this patch series.=20 > > Is there a major change that you would like to see in here? > >=20 > > Thanks a lot for your support, > > Best regards, > > -Fred >=20 > Walfred, >=20 > The only thing I'm still somewhat unhappy about the fact that this introd= uces the "bndNraw" register names in addition to the "bndN" > names. I think having both the "raw" and "cooked" variants present in GD= B's user interface will be confusing. But it is hard to decide what the ri= ght interface is for a feature that isn't available in hardware yet and peo= ple don't really have any experience with debugging code that uses MPX. >=20 > Intel GmbH > Dornacher Strasse 1 > 85622 Feldkirchen/Muenchen, Deutschland Sitz der Gesellschaft:=20 > Feldkirchen bei Muenchen > Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas=20 > Lusk > Registergericht: Muenchen HRB 47456 > Ust.-IdNr./VAT Registration No.: DE129385895 Citibank Frankfurt a.M.=20 > (BLZ 502 109 00) 600119052 >=20 > Intel GmbH > Dornacher Strasse 1 > 85622 Feldkirchen/Muenchen, Deutschland Sitz der Gesellschaft:=20 > Feldkirchen bei Muenchen > Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas=20 > Lusk > Registergericht: Muenchen HRB 47456 > Ust.-IdNr./VAT Registration No.: DE129385895 Citibank Frankfurt a.M.=20 > (BLZ 502 109 00) 600119052 >=20 >=20 >=20 Intel GmbH Dornacher Strasse 1 85622 Feldkirchen/Muenchen, Deutschland Sitz der Gesellschaft: Feldkirchen bei Muenchen Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk Registergericht: Muenchen HRB 47456 Ust.-IdNr./VAT Registration No.: DE129385895 Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052