From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23651 invoked by alias); 21 Oct 2013 11:33:02 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 23588 invoked by uid 89); 21 Oct 2013 11:33:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mga14.intel.com Received: from mga14.intel.com (HELO mga14.intel.com) (143.182.124.37) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 21 Oct 2013 11:33:00 +0000 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga102.ch.intel.com with ESMTP; 21 Oct 2013 04:32:57 -0700 X-ExtLoop1: 1 Received: from irsmsx102.ger.corp.intel.com ([163.33.3.155]) by azsmga001.ch.intel.com with ESMTP; 21 Oct 2013 04:32:54 -0700 Received: from irsmsx105.ger.corp.intel.com (163.33.3.28) by IRSMSX102.ger.corp.intel.com (163.33.3.155) with Microsoft SMTP Server (TLS) id 14.3.123.3; Mon, 21 Oct 2013 12:32:39 +0100 Received: from irsmsx104.ger.corp.intel.com ([169.254.5.89]) by IRSMSX105.ger.corp.intel.com ([169.254.7.75]) with mapi id 14.03.0123.003; Mon, 21 Oct 2013 12:32:39 +0100 From: "Tedeschi, Walfred" To: Mark Kettenis CC: "tromey@redhat.com" , "gdb-patches@sourceware.org" Subject: RE: [PATCH V7 0/8] Intel(R) MPX register support Date: Mon, 21 Oct 2013 11:33:00 -0000 Message-ID: References: <1381320034-4092-1-git-send-email-walfred.tedeschi@intel.com> <201310201923.r9KJN3O2018018@glazunov.sibelius.xs4all.nl> In-Reply-To: <201310201923.r9KJN3O2018018@glazunov.sibelius.xs4all.nl> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2013-10/txt/msg00618.txt.bz2 Mark, Our internal users of MPX found it useful to see the raw value, processed v= alues and size together. They found out that it was really handy to avoid doing the complement of on= e for every bound manipulation. (I our first patch we changed the type system to add a complement of one ty= pe, but this was considered overkill) In this sense we would like still to display the bounds on a friendly manne= r to the user. When I say friendly I mean displaying values that are meanin= gful to the user. ->Lower and upper bound should be presented as address format.=20 ->No additional manipulation needed to calculate the upper bound limit. On the other hand we could add the nice display on the python script and el= iminate the pseudo register set, having only "bndN". Would you be ok with such a change? (Having the pretty print only on the python side and eliminating the bndraw= s) Thanks and regards, -Fred. PS: You might use SDE to have an idea how it looks like. http://software.intel.com/en-us/articles/using-intel-mpx-with-the-intel-sof= tware-development-emulator http://software.intel.com/en-us/articles/intel-software-development-emulator -----Original Message----- From: gdb-patches-owner@sourceware.org [mailto:gdb-patches-owner@sourceware= .org] On Behalf Of Mark Kettenis Sent: Sunday, October 20, 2013 9:23 PM To: Tedeschi, Walfred Cc: tromey@redhat.com; gdb-patches@sourceware.org; Tedeschi, Walfred Subject: Re: [PATCH V7 0/8] Intel(R) MPX register support > From: Walfred Tedeschi > Cc: gdb-patches@sourceware.org, Walfred Tedeschi=20 > >=20 > Mark and all, >=20 > I have noticed no feedback on this patch series.=20 > Is there a major change that you would like to see in here? >=20 > Thanks a lot for your support, > Best regards, > -Fred Walfred, The only thing I'm still somewhat unhappy about the fact that this introduc= es the "bndNraw" register names in addition to the "bndN" names. I think having both the "raw" and "cooked" variants present in GDB'= s user interface will be confusing. But it is hard to decide what the righ= t interface is for a feature that isn't available in hardware yet and peopl= e don't really have any experience with debugging code that uses MPX. Intel GmbH Dornacher Strasse 1 85622 Feldkirchen/Muenchen, Deutschland Sitz der Gesellschaft: Feldkirchen bei Muenchen Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk Registergericht: Muenchen HRB 47456 Ust.-IdNr./VAT Registration No.: DE129385895 Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052