From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 18484 invoked by alias); 22 Aug 2013 09:42:21 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 18469 invoked by uid 89); 22 Aug 2013 09:42:21 -0000 X-Spam-SWARE-Status: No, score=-8.3 required=5.0 tests=BAYES_00,KHOP_THREADED,RCVD_IN_HOSTKARMA_W,RCVD_IN_HOSTKARMA_WL,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 Received: from mga01.intel.com (HELO mga01.intel.com) (192.55.52.88) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Thu, 22 Aug 2013 09:42:20 +0000 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 22 Aug 2013 02:42:18 -0700 X-ExtLoop1: 1 Received: from irsmsx101.ger.corp.intel.com ([163.33.3.153]) by fmsmga002.fm.intel.com with ESMTP; 22 Aug 2013 02:42:17 -0700 Received: from irsmsx106.ger.corp.intel.com (163.33.3.31) by IRSMSX101.ger.corp.intel.com (163.33.3.153) with Microsoft SMTP Server (TLS) id 14.3.123.3; Thu, 22 Aug 2013 10:42:16 +0100 Received: from irsmsx104.ger.corp.intel.com ([169.254.5.157]) by IRSMSX106.ger.corp.intel.com ([169.254.8.233]) with mapi id 14.03.0123.003; Thu, 22 Aug 2013 10:42:16 +0100 From: "Tedeschi, Walfred" To: "Tedeschi, Walfred" , Mark Kettenis CC: "tromey@redhat.com" , "jan.kratochvil@redhat.com" , "gdb-patches@sourceware.org" Subject: RE: [PATCH 0/7] Intel(R) MPX registers support. Date: Thu, 22 Aug 2013 09:42:00 -0000 Message-ID: References: <1377089148-11844-1-git-send-email-walfred.tedeschi@intel.com> <201308211433.r7LEXaQ9000855@glazunov.sibelius.xs4all.nl> In-Reply-To: Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SW-Source: 2013-08/txt/msg00623.txt.bz2 Hello Mark, First of all thanks for your quick response! I am not sure if I understood your question right. I understood that you would like to have it at the bottom of the list always since it is a fake register. Is this right? In the current implementation, all numbers taken cannot be renumbered in upcoming new features or extensions. Only taking new slots is possible. In the case of the mentioned register it was already taken for amd64-linux. Please correct me if I am wrong here. ;) Cheers -Fred PS: Sorry for the spam, my message was sent encrypted before. -----Original Message----- From: Mark Kettenis [mailto:mark.kettenis@xs4all.nl] Sent: Wednesday, August 21, 2013 4:34 PM To: Tedeschi, Walfred Cc: tromey@redhat.com; jan.kratochvil@redhat.com; mark.kettenis@xs4all.nl; gdb-patches@sourceware.org; Tedeschi, Walfred Subject: Re: [PATCH 0/7] Intel(R) MPX registers support. > From: Walfred Tedeschi > Date: Wed, 21 Aug 2013 14:45:41 +0200 > > This patch series adds support for the Intel(R) Memory Protection > Extension MPX registers. Native and remote debugging are covered by this patch. > > New registers are bound registers known as bnd register (bnd0...bnd3), > a config register bndcfgu and a status register bndstatus. Bound > registers store pointer bounds, i.e. bound limits of a pointer. > Bndstatus and bndcfgu store information of the current status and > configuration of other MPX counterparts. For more information [1][2]. > > Design notes: > Bound register are represented in hardware as two fields of 64bits > each, both in 64bit and 32bit mode. The fields are lower bound and upper bound. > Upper bound value is a complement of one value of the upper limiting > address. To take this into account the bnd0...bnd3 are created as > pseudo registers while the hardware values are stored on bnd0raw...bnd3raw. > > Ok to commit? Hi Walfred, I had a quick look at the diffs. Generally looks good. There is an issue though with how you handled the Linux-specific "orig_[er]ax" fake register in the GDB interal register mapping. Can you change things such that it remains at the very hand of the internal register file? I may not be able to do a full review of the changes in the next 2.5 weeks. A friendly reminder somewhere after Sep 9 wouldn't hurt ;). Cheers, Mark Intel GmbH Dornacher Strasse 1 85622 Feldkirchen/Muenchen, Deutschland Sitz der Gesellschaft: Feldkirchen bei Muenchen Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk Registergericht: Muenchen HRB 47456 Ust.-IdNr./VAT Registration No.: DE129385895 Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052