From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16136 invoked by alias); 27 May 2010 06:49:27 -0000 Received: (qmail 16116 invoked by uid 22791); 27 May 2010 06:49:25 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE X-Spam-Check-By: sourceware.org Received: from mail-px0-f169.google.com (HELO mail-px0-f169.google.com) (209.85.212.169) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 27 May 2010 06:49:19 +0000 Received: by pxi12 with SMTP id 12so7311853pxi.0 for ; Wed, 26 May 2010 23:49:16 -0700 (PDT) Received: by 10.143.26.20 with SMTP id d20mr6473142wfj.31.1274942956349; Wed, 26 May 2010 23:49:16 -0700 (PDT) MIME-Version: 1.0 Received: by 10.143.45.13 with HTTP; Wed, 26 May 2010 23:48:56 -0700 (PDT) In-Reply-To: References: <200912241738.19780.pedro@codesourcery.com> <201001081624.12634.pedro@codesourcery.com> From: Hui Zhu Date: Thu, 27 May 2010 06:51:00 -0000 Message-ID: Subject: Re: [RFC] Add support of software single step to process record To: Pedro Alves , ping huang , shuchang zhou Cc: gdb-patches@sourceware.org, Joel Brobecker , Michael Snyder , paawan oza , Tom Tromey Content-Type: multipart/mixed; boundary=001636e0af2d05bd4a04878dca71 X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2010-05/txt/msg00629.txt.bz2 --001636e0af2d05bd4a04878dca71 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Content-length: 8395 On Tue, May 25, 2010 at 11:04, Hui Zhu wrote: > Thanks Pedro. > > On Sat, Jan 9, 2010 at 00:24, Pedro Alves wrote: >> On Monday 04 January 2010 14:23:21, Hui Zhu wrote: >>> Sorry guys, the prev patch is so ugly. >> >> :-) >> >>> Thanks for teach me clear about the gdbarch_software_single_step, Pedro. >>> I did some extend with your idea. =A0Because record_wait need >>> record_resume_step point out this resume is signal step or continue. >>> >>> =A0 =A0 =A0 if (!step) >>> =A0 =A0 =A0 =A0 { >>> =A0 =A0 =A0 =A0 =A0 /* This is not hard single step. =A0*/ >>> =A0 =A0 =A0 =A0 =A0 if (!gdbarch_software_single_step_p (gdbarch)) >>> =A0 =A0 =A0 =A0 =A0 =A0 { >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* This is a normal continue. =A0*/ >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 step =3D 1; >>> =A0 =A0 =A0 =A0 =A0 =A0 } >>> =A0 =A0 =A0 =A0 =A0 else >>> =A0 =A0 =A0 =A0 =A0 =A0 { >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* This arch support soft sigle step. =A0*/ >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (single_step_breakpoints_inserted ()) >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 { >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* This is a soft single step. =A0*/ >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 record_resume_step =3D 1; >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 } >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 else >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 { >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* This is a continue. >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Try to insert a soft single = step breakpoint. =A0*/ >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (!gdbarch_software_single_step (= gdbarch, >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0get_current_frame ())) >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 { >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* This system don't want u= se soft single step. >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Use hard sigle step.= =A0*/ >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 step =3D 1; >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 } >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 } >>> =A0 =A0 =A0 =A0 =A0 =A0 } >>> =A0 =A0 =A0 =A0 } >> >> Cool, this looks pretty clear to me now. =A0Thanks. >> >> >> >>> @@ -1077,6 +1111,7 @@ record_wait (struct target_ops *ops, >>> =A0 =A0 =A0 =A0 =A0 /* This is not a single step. =A0*/ >>> =A0 =A0 =A0 =A0 =A0 ptid_t ret; >>> =A0 =A0 =A0 =A0 =A0 CORE_ADDR tmp_pc; >>> + =A0 =A0 =A0 =A0 =A0struct gdbarch *gdbarch =3D target_thread_architec= ture (inferior_ptid); >>> >>> =A0 =A0 =A0 =A0 =A0 while (1) >>> =A0 =A0 =A0 =A0 =A0 =A0 { >>> @@ -1099,6 +1134,9 @@ record_wait (struct target_ops *ops, >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 tmp_pc =3D regcache_read_pc (regcac= he); >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 aspace =3D get_regcache_aspace (reg= cache); >>> >>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (gdbarch_software_single_step_p= (gdbarch)) >>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0remove_single_step_breakpoints= (); >> >> This will gdb_assert inside remove_single_step_breakpoints >> if SSS bkpts are not inserted, but gdbarch_software_single_step_p >> returns true. =A0This instead is safer: >> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (single_step_breakpoints_inserted = ()) >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0remove_single_step_breakpoints (); > > OK. =A0I will fix it. > >> >> But, what if it was infrun that had inserted the single-step >> breakpoints, for a "next" or "step", etc.? =A0Shouldn't you check >> for record_resume_step too? >> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (!record_resume_step && single_step_break= points_inserted ()) >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 remove_single_step_breakpoints (); >> >> Otherwise, the check below for >> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0else if (breakpoint_inserted_here_p (= aspace, tmp_pc)) >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0{ >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* There is a breakpoint here= . =A0Let the core >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 handle it. =A0*/ >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (software_breakpoint_inser= ted_here_p (aspace, tmp_pc)) >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0{ >> >> would fail, and the finished single-step wouldn't be reported to the >> core, right? > > I think this single step will be handle by line: > =A0 =A0 =A0if (record_resume_step) > =A0 =A0 =A0 =A0{ > =A0 =A0 =A0 =A0 =A0/* This is a single step. =A0*/ > =A0 =A0 =A0 =A0 =A0return record_beneath_to_wait (record_beneath_to_wait_= ops, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 ptid, status, options); > =A0 =A0 =A0 =A0} > >> >> >> Lastly, you may also want to confirm that the SSS bkpt managed by record= .d itself explains the SIGTRAP before removing before issueing another >> single-step. =A0If any unexplainable SIGTRAP happens for any reason while >> single-stepping, you should report it to infrun instead. =A0In other wor= ds: >> >> With software single-stepping, we can distinguish most random >> SIGTRAPs from SSS SIGTRAPs, so: >> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* This must be a single-step= trap. =A0Record the >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 insn and issue another s= tep. =A0*/ >> >> ... the "must" here ends up being a bit too strong. =A0I'd certainly >> understand ignoring this for simplicity or performance reasons though. > > Ah. =A0Looks we didn't have good way to handle it. =A0I change this comme= nt to: > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* This is a single-step trap.= =A0Record the > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 insn and issue another st= ep. > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FIXME: this part can be a= random SIGTRAP too. > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 But GDB cannot handle it.= =A0*/ > > > Shuchang, =A0could you try your code just use command si and > reverse-xxx. =A0If that part OK. =A0Please help me try this patch. > > Ping, please help me test this patch. =A0And about hellogcc, you can find= us in: > https://groups.google.com/group/hellogcc > https://webchat.freenode.net/ #hellogcc > > Thanks, > Hui > > 2010-05-25 =A0Hui Zhu =A0 > > =A0 =A0 =A0 =A0* breakpoint.c (single_step_breakpoints_inserted): New > =A0 =A0 =A0 =A0function. > =A0 =A0 =A0 =A0* breakpoint.h (single_step_breakpoints_inserted): Extern. > =A0 =A0 =A0 =A0* record.c (record_resume): Add code for software single s= tep. > =A0 =A0 =A0 =A0(record_wait): Ditto. > Hello, After do some test with Ping, I found some trouble and fixed them. 1. Add following: @@ -1134,8 +1176,20 @@ record_wait (struct target_ops *ops, break; } + if (gdbarch_software_single_step_p (gdbarch)) + { + /* Try to insert the software single step breakpoint. + If insert success, set step to 0. */ + set_executing (inferior_ptid, 0); + reinit_frame_cache (); + if (gdbarch_software_single_step (gdbarch, + get_current_frame ())) + step =3D 0; + set_executing (inferior_ptid, 1); + } This is because in record_wait, we cannot call get_current_frame () directly. And the frame message need refresh each exec cycle. 2. Ping found that reverse-exec cannot single step in RISC board. That is because "gdbarch_software_single_step" just can insert the breakpoint to the next addr. So I add following: @@ -1436,7 +1436,8 @@ maybe_software_singlestep (struct gdbarc { int hw_step =3D 1; - if (gdbarch_software_single_step_p (gdbarch) + if (execution_direction =3D=3D EXEC_FORWARD + && gdbarch_software_single_step_p (gdbarch) && gdbarch_software_single_step (gdbarch, get_current_frame ())) If reverse, gdb will not user sss breakpoint to single step. 3. Ping got some gdb_assert in sometime. And I am not close to his board. So I didn't know what happen. So I add following: @@ -1534,7 +1535,8 @@ a command like `return' or `jump' to con /* If STEP is set, it's a request to use hardware stepping facilities. But in that case, we should never use singlestep breakpoint. */ - gdb_assert (!(singlestep_breakpoints_inserted_p && step)); + gdb_assert (!(execution_direction =3D=3D EXEC_FORWARD + && singlestep_breakpoints_inserted_p && step)); The lost one still need be test. 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