From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 103396 invoked by alias); 1 Oct 2018 09:49:47 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 103384 invoked by uid 89); 1 Oct 2018 09:49:45 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.8 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPF_PASS autolearn=ham version=3.3.2 spammy=backwards X-HELO: mga11.intel.com Received: from mga11.intel.com (HELO mga11.intel.com) (192.55.52.93) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 01 Oct 2018 09:49:44 +0000 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Oct 2018 02:49:42 -0700 Received: from irsmsx106.ger.corp.intel.com ([163.33.3.31]) by orsmga001.jf.intel.com with ESMTP; 01 Oct 2018 02:49:41 -0700 Received: from irsmsx104.ger.corp.intel.com ([169.254.5.213]) by IRSMSX106.ger.corp.intel.com ([169.254.8.45]) with mapi id 14.03.0319.002; Mon, 1 Oct 2018 10:49:40 +0100 From: "Metzger, Markus T" To: Simon Marchi , "gdb-patches@sourceware.org" Subject: RE: [PATCH] Fix is_amd64_regs_target check in i386-avx512.exp Date: Mon, 01 Oct 2018 09:49:00 -0000 Message-ID: References: <20180928204114.20491-1-simon.marchi@ericsson.com> In-Reply-To: <20180928204114.20491-1-simon.marchi@ericsson.com> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2018-10/txt/msg00008.txt.bz2 Hello Simon, > As reported by Jan here: >=20 > https://sourceware.org/ml/gdb-patches/2018-09/msg00831.html >=20 > the check that sets the number of available registers seems backwards. > I can't test this patch however, since I don't have access to a cpu with = AVX512. > Could somebody perhaps from Intel, or somebody else that has access to su= ch > CPU, take a look? It indeed is backwards. The current test fails badly when run with -m32. =20 > gdb/testsuite/ChangeLog: >=20 > * gdb.arch/i386-avx512.exp: Fix setting of nr_regs based on > is_amd64_regs_target. > --- > gdb/testsuite/gdb.arch/i386-avx512.exp | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) >=20 > diff --git a/gdb/testsuite/gdb.arch/i386-avx512.exp > b/gdb/testsuite/gdb.arch/i386-avx512.exp > index de2f62c3e1f..f27af534cfd 100644 > --- a/gdb/testsuite/gdb.arch/i386-avx512.exp > +++ b/gdb/testsuite/gdb.arch/i386-avx512.exp > @@ -93,9 +93,9 @@ gdb_test "break [gdb_get_line_number "third breakpoint > here"]" \ gdb_continue_to_breakpoint "continue to third breakpoint in ma= in" >=20 > if [is_amd64_regs_target] { > - set nr_regs 8 > -} else { > set nr_regs 32 > +} else { > + set nr_regs 8 > } >=20 > for { set r 0 } { $r < $nr_regs } { incr r } { > -- > 2.19.0 With your patch, the test only fails for zmm registers due to broken XSAVE handling. This is fixed by Jan's patch. With both patches together, the t= est passes for -m32. Regards, Markus. Intel Deutschland GmbH Registered Address: Am Campeon 10-12, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Christin Eisenschmid, Christian Lamprechter Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928