From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 115144 invoked by alias); 23 May 2017 14:11:06 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 115122 invoked by uid 89); 23 May 2017 14:11:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.6 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 spammy=nicole, sk:markus, Trace, Munich X-HELO: mga02.intel.com Received: from mga02.intel.com (HELO mga02.intel.com) (134.134.136.20) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 23 May 2017 14:11:02 +0000 Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 May 2017 07:11:00 -0700 X-ExtLoop1: 1 Received: from irsmsx107.ger.corp.intel.com ([163.33.3.99]) by orsmga004.jf.intel.com with ESMTP; 23 May 2017 07:10:59 -0700 Received: from irsmsx104.ger.corp.intel.com ([169.254.5.170]) by IRSMSX107.ger.corp.intel.com ([169.254.10.107]) with mapi id 14.03.0319.002; Tue, 23 May 2017 15:10:58 +0100 From: "Metzger, Markus T" To: "gdb-patches@sourceware.org" Subject: RE: [PATCH 3/3] btrace: support decoder events Date: Tue, 23 May 2017 14:11:00 -0000 Message-ID: References: <1493390658-22342-1-git-send-email-markus.t.metzger@intel.com> <1493390658-22342-3-git-send-email-markus.t.metzger@intel.com> In-Reply-To: <1493390658-22342-3-git-send-email-markus.t.metzger@intel.com> dlp-product: dlpe-windows dlp-version: 10.0.102.7 dlp-reaction: no-action Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2017-05/txt/msg00508.txt.bz2 Ping. Thanks, Markus. > -----Original Message----- > From: gdb-patches-owner@sourceware.org [mailto:gdb-patches- > owner@sourceware.org] On Behalf Of Markus Metzger > Sent: Friday, April 28, 2017 4:44 PM > To: gdb-patches@sourceware.org > Subject: [PATCH 3/3] btrace: support decoder events >=20 > Newer versions of libipt support instruction flow decoder events instead = of > indicating those events with flags in struct pt_insn. Add support for th= em in > GDB. >=20 > 2017-04-28 Markus Metzger >=20 > gdb/ > * btrace.c (handle_pt_insn_events): New. > (ftrace_add_pt): Call handle_pt_insn_events. Rename ERRCODE into > STATUS. Split into this and ... > (handle_pt_insn_event_flags): ... this. >=20 >=20 > --- > gdb/btrace.c | 174 +++++++++++++++++++++++++++++++++++++++++++----------= --- > --- > 1 file changed, 127 insertions(+), 47 deletions(-) >=20 > diff --git a/gdb/btrace.c b/gdb/btrace.c > index 6780e22..21d0be9 100644 > --- a/gdb/btrace.c > +++ b/gdb/btrace.c > @@ -1132,6 +1132,116 @@ pt_btrace_insn (const struct pt_insn &insn) > pt_btrace_insn_flags (insn)}; > } >=20 > +/* Handle instruction decode events (libipt-v2). */ > + > +static int > +handle_pt_insn_events (struct pt_insn_decoder *decoder, > + struct btrace_function **pbegin, > + struct btrace_function **pend, > + VEC (bfun_s) **gaps, int status) > +{ > +#if defined (HAVE_PT_INSN_EVENT) > + while (status & pts_event_pending) > + { > + struct pt_event event; > + uint64_t offset; > + > + status =3D pt_insn_event (decoder, &event, sizeof (event)); > + if (status < 0) > + break; > + > + switch (event.type) > + { > + default: > + break; > + > + case ptev_enabled: > + if (*pbegin !=3D NULL && event.variant.enabled.resumed =3D=3D 0) > + { > + *pend =3D ftrace_new_gap (*pend, BDE_PT_DISABLED); > + if (*pbegin =3D=3D NULL) > + *pbegin =3D *pend; > + > + VEC_safe_push (bfun_s, *gaps, *pend); > + > + pt_insn_get_offset (decoder, &offset); > + > + warning (_("Non-contiguous trace at instruction %u (offset =3D 0x= %" > + PRIx64 ")."), (*pend)->insn_offset - 1, offset); > + } > + > + break; > + > + case ptev_overflow: > + *pend =3D ftrace_new_gap (*pend, BDE_PT_OVERFLOW); > + if (*pbegin =3D=3D NULL) > + *pbegin =3D *pend; > + > + VEC_safe_push (bfun_s, *gaps, *pend); > + > + pt_insn_get_offset (decoder, &offset); > + > + warning (_("Overflow at instruction %u (offset =3D 0x%" PRIx64 ")."), > + (*pend)->insn_offset - 1, offset); > + > + break; > + } > + } > +#endif /* defined (HAVE_PT_INSN_EVENT) */ > + > + return status; > +} > + > +/* Handle events indicated by flags in INSN (libipt-v1). */ > + > +static void > +handle_pt_insn_event_flags (struct pt_insn_decoder *decoder, > + const struct pt_insn *insn, > + struct btrace_function **pbegin, > + struct btrace_function **pend, > + VEC (bfun_s) **gaps) > +{ > +#if defined (HAVE_STRUCT_PT_INSN_ENABLED) > + /* Tracing is disabled and re-enabled each time we enter the kernel. = Most > + times, we continue from the same instruction we stopped before. Th= is is > + indicated via the RESUMED instruction flag. The ENABLED instructio= n flag > + means that we continued from some other instruction. Indicate this= as a > + trace gap except when tracing just started. */ > + if (insn.enabled && (*begin !=3D NULL)) > + { > + uint64_t offset; > + > + *end =3D ftrace_new_gap (*end, BDE_PT_DISABLED); > + > + VEC_safe_push (bfun_s, *gaps, *end); > + > + pt_insn_get_offset (decoder, &offset); > + > + warning (_("Non-contiguous trace at instruction %u (offset =3D 0x%= " PRIx64 > + ", pc =3D 0x%" PRIx64 ")."), (*end)->insn_offset - 1, offset, > + insn.ip); > + } > +#endif /* defined (HAVE_STRUCT_PT_INSN_ENABLED) */ > + > +#if defined (HAVE_STRUCT_PT_INSN_RESYNCED) > + /* Indicate trace overflows. */ > + if (insn.resynced) > + { > + uint64_t offset; > + > + *end =3D ftrace_new_gap (*end, BDE_PT_OVERFLOW); > + if (*begin =3D=3D NULL) > + *begin =3D *end; > + > + VEC_safe_push (bfun_s, *gaps, *end); > + > + pt_insn_get_offset (decoder, &offset); > + > + warning (_("Overflow at instruction %u (offset =3D 0x%" PRIx64 ", = pc =3D 0x%" > + PRIx64 ")."), (*end)->insn_offset - 1, offset, insn.ip); > + } > +#endif /* defined (HAVE_STRUCT_PT_INSN_RESYNCED) */ > +} >=20 > /* Add function branch trace using DECODER. */ >=20 > @@ -1142,64 +1252,34 @@ ftrace_add_pt (struct pt_insn_decoder *decoder, > VEC (bfun_s) **gaps) > { > uint64_t offset; > - int errcode; > + int status; >=20 > for (;;) > { > struct pt_insn insn; >=20 > - errcode =3D pt_insn_sync_forward (decoder); > - if (errcode < 0) > + status =3D pt_insn_sync_forward (decoder); > + if (status < 0) > { > - if (errcode !=3D -pte_eos) > + if (status !=3D -pte_eos) > warning (_("Failed to synchronize onto the Intel Processor " > - "Trace stream: %s."), pt_errstr (pt_errcode (errcode))); > + "Trace stream: %s."), pt_errstr (pt_errcode (status))); > break; > } >=20 > for (;;) > { > - errcode =3D pt_insn_next (decoder, &insn, sizeof(insn)); > - if (errcode < 0) > + /* Handle events from the previous iteration or synchronization. */ > + status =3D handle_pt_insn_events (decoder, begin, end, gaps, status); > + if (status < 0) > break; >=20 > - /* Look for gaps in the trace - unless we're at the beginning. */ > - if (*begin !=3D NULL) > - { > - /* Tracing is disabled and re-enabled each time we enter the > - kernel. Most times, we continue from the same instruction we > - stopped before. This is indicated via the RESUMED instruction > - flag. The ENABLED instruction flag means that we continued > - from some other instruction. Indicate this as a trace gap. */ > - if (insn.enabled) > - { > - *end =3D ftrace_new_gap (*end, BDE_PT_DISABLED); > - > - VEC_safe_push (bfun_s, *gaps, *end); > - > - pt_insn_get_offset (decoder, &offset); > - > - warning (_("Non-contiguous trace at instruction %u (offset " > - "=3D 0x%" PRIx64 ", pc =3D 0x%" PRIx64 ")."), > - (*end)->insn_offset - 1, offset, insn.ip); > - } > - } > - > - /* Indicate trace overflows. */ > - if (insn.resynced) > - { > - *end =3D ftrace_new_gap (*end, BDE_PT_OVERFLOW); > - if (*begin =3D=3D NULL) > - *begin =3D *end; > - > - VEC_safe_push (bfun_s, *gaps, *end); > - > - pt_insn_get_offset (decoder, &offset); > + status =3D pt_insn_next (decoder, &insn, sizeof(insn)); > + if (status < 0) > + break; >=20 > - warning (_("Overflow at instruction %u (offset =3D 0x%" PRIx64 > - ", pc =3D 0x%" PRIx64 ")."), (*end)->insn_offset - 1, > - offset, insn.ip); > - } > + /* Handle events indicated by flags in INSN. */ > + handle_pt_insn_event_flags (decoder, &insn, begin, end, gaps); >=20 > *end =3D ftrace_update_function (*end, insn.ip); > if (*begin =3D=3D NULL) > @@ -1212,11 +1292,11 @@ ftrace_add_pt (struct pt_insn_decoder *decoder, > ftrace_update_insns (*end, &btinsn); > } >=20 > - if (errcode =3D=3D -pte_eos) > + if (status =3D=3D -pte_eos) > break; >=20 > /* Indicate the gap in the trace. */ > - *end =3D ftrace_new_gap (*end, errcode); > + *end =3D ftrace_new_gap (*end, status); > if (*begin =3D=3D NULL) > *begin =3D *end; >=20 > @@ -1225,9 +1305,9 @@ ftrace_add_pt (struct pt_insn_decoder *decoder, > pt_insn_get_offset (decoder, &offset); >=20 > warning (_("Decode error (%d) at instruction %u (offset =3D 0x%" P= RIx64 > - ", pc =3D 0x%" PRIx64 "): %s."), errcode, > + ", pc =3D 0x%" PRIx64 "): %s."), status, > (*end)->insn_offset - 1, offset, insn.ip, > - pt_errstr (pt_errcode (errcode))); > + pt_errstr (pt_errcode (status))); > } > } >=20 > -- > 1.8.3.1 Intel Deutschland GmbH Registered Address: Am Campeon 10-12, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Christin Eisenschmid, Christian Lamprechter Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928