From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 128880 invoked by alias); 6 Aug 2015 15:00:43 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 128870 invoked by uid 89); 6 Aug 2015 15:00:42 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mga02.intel.com Received: from mga02.intel.com (HELO mga02.intel.com) (134.134.136.20) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 06 Aug 2015 15:00:41 +0000 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP; 06 Aug 2015 08:00:39 -0700 X-ExtLoop1: 1 Received: from irsmsx101.ger.corp.intel.com ([163.33.3.153]) by fmsmga001.fm.intel.com with ESMTP; 06 Aug 2015 08:00:36 -0700 Received: from irsmsx111.ger.corp.intel.com (10.108.20.4) by IRSMSX101.ger.corp.intel.com (163.33.3.153) with Microsoft SMTP Server (TLS) id 14.3.224.2; Thu, 6 Aug 2015 16:00:35 +0100 Received: from irsmsx104.ger.corp.intel.com ([169.254.5.131]) by irsmsx111.ger.corp.intel.com ([169.254.2.31]) with mapi id 14.03.0224.002; Thu, 6 Aug 2015 16:00:35 +0100 From: "Metzger, Markus T" To: Pedro Alves CC: "gdb-patches@sourceware.org" Subject: RE: [PATCH] configure: check for perf_event.h version Date: Thu, 06 Aug 2015 15:00:00 -0000 Message-ID: References: <1438866405-22616-1-git-send-email-markus.t.metzger@intel.com> <55C365B2.4010906@redhat.com> <55C36F31.5080807@redhat.com> In-Reply-To: <55C36F31.5080807@redhat.com> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2015-08/txt/msg00154.txt.bz2 > -----Original Message----- > From: Pedro Alves [mailto:palves@redhat.com] > Sent: Thursday, August 6, 2015 4:29 PM > To: Metzger, Markus T > Cc: gdb-patches@sourceware.org > Subject: Re: [PATCH] configure: check for perf_event.h version >=20 > On 08/06/2015 03:14 PM, Metzger, Markus T wrote: > >> -----Original Message----- > >> From: Pedro Alves [mailto:palves@redhat.com] > >> Sent: Thursday, August 6, 2015 3:49 PM > >> To: Metzger, Markus T > >> Cc: gdb-patches@sourceware.org > >> Subject: Re: [PATCH] configure: check for perf_event.h version > >> > >> On 08/06/2015 02:06 PM, Markus Metzger wrote: > >>> Intel(R) Processor Trace support requires a recent linux/perf_event.h > >> header. > >>> > >>> When GDB is built on an older system, Intel(R) Processor Trace will n= ot > be > >>> available and there is no indication in the configure and build log a= s to > >>> what went wrong. > >>> > >>> Check for a compatible linux/perf_event.h at configure-time. > >> > >> > >>> diff --git a/gdb/configure.ac b/gdb/configure.ac > >>> index 905c27b..d867e85 100644 > >>> --- a/gdb/configure.ac > >>> +++ b/gdb/configure.ac > >>> @@ -1252,6 +1252,20 @@ if test "${with_intel_pt}" =3D no; then > >>> AC_MSG_WARN([Intel(R) Processor Trace support disabled; some > >> features may be unavailable.]) > >>> HAVE_LIBIPT=3Dno > >>> else > >>> + AC_PREPROC_IFELSE(AC_LANG_SOURCE([[ > >>> +#include > >>> +#ifdef PERF_ATTR_SIZE_VER5 > >>> +# error > >>> +#endif > >> > >> Can you explain what kind of symbol PERF_ATTR_SIZE_VER5 is? > >> From the patch, I understand that that is something that is _not_ > >> defined in the perf versions that are supposedly supported? > >> (otherwise, I'd expect an #ifndef instead.) > > > > It's a macro. >=20 > Was there ever a PERF_ATTR_SIZE_VER4 symbol? What if > PERF_ATTR_SIZE_VER6 is ever created? Do we want to have to > check for it explicitly then? The linux/perf_event.h header defines the macros for all previous versions. The current version thus defines #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ /* add: sample_stack_user */ #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ > > I took the double-negation approach from a similar > > check for python_has_threads. >=20 > In the python case, we've already checked earlier that python.h > is available. >=20 > In your case, it seems that if isn't > available, you end up with perf_event=3Dyes? Is that what we want? No. I'll change it and send an update. Thanks, Markus. Intel Deutschland GmbH Registered Address: Am Campeon 10-12, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Christin Eisenschmid, Prof. Dr. Hermann Eul Chairperson of the Supervisory Board: Tiffany Doon Silva Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928