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[24.4.73.83]) by smtp.gmail.com with ESMTPSA id p14sm3670693pjb.9.2021.11.09.16.01.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Nov 2021 16:01:08 -0800 (PST) X-Google-Original-From: Vineet Gupta Subject: Re: [PATCH] sim: riscv: fix build breakage with rvv changes To: Vineet Gupta , gdb-patches@sourceware.org, binutils@sourceware.org Newsgroups: gmane.comp.gnu.binutils,gmane.comp.gdb.patches References: <20211029192856.3987778-1-vineetg@rivosinc.com> Message-ID: <9e1f4322-5ca3-a12e-abb7-83ee59cdace1@linux.dev> Date: Tue, 9 Nov 2021 16:01:05 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20211029192856.3987778-1-vineetg@rivosinc.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Vineet Gupta via Gdb-patches Reply-To: Vineet Gupta Cc: Dylan Reid , Kito Cheng Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" ping ! On 10/29/21 12:28 PM, Vineet Gupta wrote: > changes to gas for riscv vector extensions need to be propagated to sim > otherwise gdb fails to build on users/riscv/binutils-integration-branch > > This patch currently applies to that branch. > > Fixes: 144cceb058e "(RISC-V/rvv: Add rvv v0.10 instructions.)" > Reported-by: Dylan Reid > Signed-off-by: Vineet Gupta > --- > sim/riscv/ChangeLog-2021 | 4 ++++ > sim/riscv/sim-main.c | 3 ++- > 2 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/sim/riscv/ChangeLog-2021 b/sim/riscv/ChangeLog-2021 > index e9aa74490f12..9ced6773bdd6 100644 > --- a/sim/riscv/ChangeLog-2021 > +++ b/sim/riscv/ChangeLog-2021 > @@ -1,3 +1,7 @@ > +2021-20-28 Vineet Gupta > + > + * sim-main.c (step_once): Fix match_func call per gas changes. > + > 2021-07-01 Mike Frysinger > > * configure: Regenerate. > diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c > index 0faf9395ae52..9b4f7c6c5aad 100644 > --- a/sim/riscv/sim-main.c > +++ b/sim/riscv/sim-main.c > @@ -956,6 +956,7 @@ void step_once (SIM_CPU *cpu) > sim_cia pc = cpu->pc; > const struct riscv_opcode *op; > int xlen = RISCV_XLEN (cpu); > + const char *error = NULL; > > if (TRACE_ANY_P (cpu)) > trace_prefix (sd, cpu, NULL_CIA, pc, TRACE_LINENUM_P (cpu), > @@ -985,7 +986,7 @@ void step_once (SIM_CPU *cpu) > for (; op->name; op++) > { > /* Does the opcode match? */ > - if (! op->match_func (op, iw)) > + if (! op->match_func (op, iw, 0, /* check_constraints */ &error)) > continue; > /* Is this a pseudo-instruction and may we print it as such? */ > if (op->pinfo & INSN_ALIAS) >