From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28475 invoked by alias); 12 Feb 2020 17:17:04 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 28464 invoked by uid 89); 12 Feb 2020 17:17:04 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-20.6 required=5.0 tests=AWL,BAYES_00,FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.1 spammy=mit X-HELO: mout.gmx.net Received: from mout.gmx.net (HELO mout.gmx.net) (212.227.17.20) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 12 Feb 2020 17:17:02 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1581527817; bh=5NE+utwEP77Y7M+hsTX8li+pKsoGTvoTN9q6q2R7Xrk=; h=X-UI-Sender-Class:Subject:From:To:Cc:References:Date:In-Reply-To; b=RgZaNjwCPOOtEqhUx/au5loTr4rmfgsEaLnMsrsr70w2+B0/7W8lCqz7cqrmyUr3O cLakIqH4XolAEuwlOMkeplnu/GPGlK+AWC8gc7VvGEOU5i/ljqg1dhRSz1MAaElogF 400TcmPhAB1ZmO91C1VAror35b3+K9krwTWETIJQ= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from [192.168.0.241] ([89.71.135.231]) by mail.gmx.com (mrgmx104 [212.227.17.174]) with ESMTPSA (Nemesis) id 1MmDEm-1jk1tJ0cfQ-00iFda; Wed, 12 Feb 2020 18:16:57 +0100 Subject: Re: [PATCH] Fix arm-netbsd build error From: Kamil Rytarowski To: Christian Biesinger , Alan Hayward Cc: gdb-patches , nd References: <20200211225503.32992-1-cbiesinger@google.com> <57C0F31A-7085-4722-93B6-062DF7A10E58@arm.com> Message-ID: <96a09009-a9c9-aad2-5a83-e08f7e8dcb68@gmx.com> Date: Wed, 12 Feb 2020 17:17:00 -0000 User-Agent: Mozilla/5.0 (X11; NetBSD amd64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="ABNQBP227S4cCLG4CwaBDumL0xGArRPHb" X-IsSubscribed: yes X-SW-Source: 2020-02/txt/msg00458.txt.bz2 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --ABNQBP227S4cCLG4CwaBDumL0xGArRPHb Content-Type: multipart/mixed; boundary="RZd6ecHIKiua8sMM87pmAURIgg3h0tqTH"; protected-headers="v1" From: Kamil Rytarowski To: Christian Biesinger , Alan Hayward Cc: gdb-patches , nd Message-ID: <96a09009-a9c9-aad2-5a83-e08f7e8dcb68@gmx.com> Subject: Re: [PATCH] Fix arm-netbsd build error References: <20200211225503.32992-1-cbiesinger@google.com> <57C0F31A-7085-4722-93B6-062DF7A10E58@arm.com> In-Reply-To: --RZd6ecHIKiua8sMM87pmAURIgg3h0tqTH Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: quoted-printable Content-length: 9511 On 12.02.2020 18:09, Kamil Rytarowski wrote: > On 12.02.2020 17:28, Christian Biesinger wrote: >> On Wed, Feb 12, 2020 at 7:29 AM Alan Hayward wrot= e: >>> >>> >>> >>>> On 11 Feb 2020, at 23:34, Christian Biesinger via gdb-patches wrote: >>>> >>>> On Tue, Feb 11, 2020 at 4:55 PM Christian Biesinger >>>> wrote: >>>>> >>>>> The floating point register interface has changed to this: >>>>> https://github.com/NetBSD/src/blob/trunk/sys/arch/arm/include/reg.h >>>>> >>>>> It now uses VFP instead of FPA registers. This patch updates >>>>> arm-nbsd-nat.c accordingly. >>>>> >>>>> Tested by compiling on arm-netbsd on qemu. For actually testing, there >>>>> seems to be something missing as "info registers" only shows FPA >>>>> registers and no VFP ones. I am still investigating why this is; >>>>> please let me know if you know. However, I think this is still good >>>>> to check in as-is. >>>> >>>> Hm... this is perhaps because arm_netbsd_nat_target does not implement >>>> read_description; if it returned arm_read_description >>>> (ARM_FP_TYPE_VFPV2) this may work? >>>> >>> >>> Yes, looks like netbsd isn=E2=80=99t using any target description funct= ionality. >>> >>> I suspect the code is getting into arm_gdbarch_init() with a null tdesc, >>> and then using the AUTO setting. But that=E2=80=99s just a guess. >>> >>> Implementing read_description as you suggest should help. However, >>> read_description should probably do HWCAP checking similar to the >>> arm_linux_nat_target and arm_fbsd_nat_target versions. >>> >>> Without that, I=E2=80=99d worry that your patch below might start writi= ng off the >>> end of the regcache that had been allocated for a fewer number of regis= ters. >> >> Hm... well, I've probably spent entirely too much time on this >> already, but just in case there's an easy fix -- Kamil, does NetBSD >> provide an API similar to Linux's HWCAP API that would let me check >> which VFP version the current CPU is using? It seems AUXV does not >> contain HWCAP data on NetBSD, unlike Linux/FreeBSD, though I may be >> missing something. >> >> (Compare arm_fbsd_read_description_auxv / >> arm_linux_nat_target::read_description) >> >> Christian >> >=20 > Thank you for your work. >=20 > HWCAP in auxv is not supported (although there is a stub for it). >=20 > Here is a complete algorithm to detect FPU on ARM 32-bit. >=20 > http://netbsd.org/~kamil/arm-fpu.c >=20 Here is another example with SIMD: http://cvsweb.netbsd.org/bsdweb.cgi/xsrc/external/mit/pixman/dist/pixman/pi= xman-arm.c.diff?r1=3D1.1&r2=3D1.2&f=3Dh >>> >>>>> >>>>> gdb/ChangeLog: >>>>> >>>>> 2020-02-11 Christian Biesinger >>>>> >>>>> * arm-nbsd-nat.c (arm_supply_fparegset): Rename to... >>>>> (arm_supply_vfpregset): ...this, and update to use VFP registe= rs. >>>>> (fetch_fp_register): Update. >>>>> (fetch_fp_regs): Update. >>>>> (store_fp_register): Update. >>>>> (store_fp_regs): Update. >>>>> (fetch_elfcore_registers): Update. >>>>> --- >>>>> gdb/arm-nbsd-nat.c | 80 ++++++++++++++++++++-------------------------- >>>>> 1 file changed, 34 insertions(+), 46 deletions(-) >>>>> >>>>> diff --git a/gdb/arm-nbsd-nat.c b/gdb/arm-nbsd-nat.c >>>>> index 11afc289c3..8027f54dfe 100644 >>>>> --- a/gdb/arm-nbsd-nat.c >>>>> +++ b/gdb/arm-nbsd-nat.c >>>>> @@ -65,15 +65,13 @@ arm_supply_gregset (struct regcache *regcache, st= ruct reg *gregset) >>>>> } >>>>> >>>>> static void >>>>> -arm_supply_fparegset (struct regcache *regcache, struct fpreg *fpare= gset) >>>>> +arm_supply_vfpregset (struct regcache *regcache, struct fpreg *fpreg= set) >>>>> { >>>>> - int regno; >>>>> - >>>>> - for (regno =3D ARM_F0_REGNUM; regno <=3D ARM_F7_REGNUM; regno++) >>>>> - regcache->raw_supply (regno, >>>>> - (char *) &fparegset->fpr[regno - ARM_F0_REG= NUM]); >>>>> + struct vfpreg &vfp =3D fpregset->fpr_vfp; >>>>> + for (int regno =3D ARM_D0_REGNUM; regno <=3D ARM_D31_REGNUM; regno= ++) >>>>> + regcache->raw_supply (regno, (char *) &vfp.vfp_regs[regno - ARM_= D0_REGNUM]); >>>>> >>>>> - regcache->raw_supply (ARM_FPS_REGNUM, (char *) &fparegset->fpr_fps= r); >>>>> + regcache->raw_supply (ARM_FPSCR_REGNUM, (char *) &vfp.vfp_fpscr); >>>>> } >>>>> >>>>> static void >>>>> @@ -147,10 +145,10 @@ static void >>>>> fetch_fp_register (struct regcache *regcache, int regno) >>>>> { >>>>> struct fpreg inferior_fp_registers; >>>>> - int ret; >>>>> + int ret =3D ptrace (PT_GETFPREGS, regcache->ptid ().pid (), >>>>> + (PTRACE_TYPE_ARG3) &inferior_fp_registers, 0); >>>>> >>>>> - ret =3D ptrace (PT_GETFPREGS, regcache->ptid ().pid (), >>>>> - (PTRACE_TYPE_ARG3) &inferior_fp_registers, 0); >>>>> + struct vfpreg &vfp =3D inferior_fp_registers.fpr_vfp; >>>>> >>>>> if (ret < 0) >>>>> { >>>>> @@ -158,18 +156,15 @@ fetch_fp_register (struct regcache *regcache, i= nt regno) >>>>> return; >>>>> } >>>>> >>>>> - switch (regno) >>>>> + if (regno =3D=3D ARM_FPSCR_REGNUM) >>>>> + regcache->raw_supply (ARM_FPSCR_REGNUM, (char *) &vfp.vfp_fpscr); >>>>> + else if (regno >=3D ARM_D0_REGNUM && regno <=3D ARM_D31_REGNUM) >>>>> { >>>>> - case ARM_FPS_REGNUM: >>>>> - regcache->raw_supply (ARM_FPS_REGNUM, >>>>> - (char *) &inferior_fp_registers.fpr_fpsr); >>>>> - break; >>>>> - >>>>> - default: >>>>> - regcache->raw_supply >>>>> - (regno, (char *) &inferior_fp_registers.fpr[regno - ARM_F0_RE= GNUM]); >>>>> - break; >>>>> + regcache->raw_supply (regno, >>>>> + (char *) &vfp.vfp_regs[regno - ARM_D0_REG= NUM]); >>>>> } >>>>> + else >>>>> + warning (_("Invalid register number.")); >>>>> } >>>>> >>>>> static void >>>>> @@ -188,7 +183,7 @@ fetch_fp_regs (struct regcache *regcache) >>>>> return; >>>>> } >>>>> >>>>> - arm_supply_fparegset (regcache, &inferior_fp_registers); >>>>> + arm_supply_vfpregset (regcache, &inferior_fp_registers); >>>>> } >>>>> >>>>> void >>>>> @@ -327,10 +322,9 @@ static void >>>>> store_fp_register (const struct regcache *regcache, int regno) >>>>> { >>>>> struct fpreg inferior_fp_registers; >>>>> - int ret; >>>>> - >>>>> - ret =3D ptrace (PT_GETFPREGS, regcache->ptid ().pid (), >>>>> - (PTRACE_TYPE_ARG3) &inferior_fp_registers, 0); >>>>> + int ret =3D ptrace (PT_GETFPREGS, regcache->ptid ().pid (), >>>>> + (PTRACE_TYPE_ARG3) &inferior_fp_registers, 0); >>>>> + struct vfpreg &vfp =3D inferior_fp_registers.fpr_vfp; >>>>> >>>>> if (ret < 0) >>>>> { >>>>> @@ -338,18 +332,15 @@ store_fp_register (const struct regcache *regca= che, int regno) >>>>> return; >>>>> } >>>>> >>>>> - switch (regno) >>>>> + if (regno =3D=3D ARM_FPSCR_REGNUM) >>>>> + regcache->raw_collect (ARM_FPSCR_REGNUM, (char *) &vfp.vfp_fpscr= ); >>>>> + else if (regno >=3D ARM_D0_REGNUM && regno <=3D ARM_D31_REGNUM) >>>>> { >>>>> - case ARM_FPS_REGNUM: >>>>> - regcache->raw_collect (ARM_FPS_REGNUM, >>>>> - (char *) &inferior_fp_registers.fpr_fpsr= ); >>>>> - break; >>>>> - >>>>> - default: >>>>> - regcache->raw_collect >>>>> - (regno, (char *) &inferior_fp_registers.fpr[regno - ARM_F0_RE= GNUM]); >>>>> - break; >>>>> + regcache->raw_collect (regno, >>>>> + (char *) &vfp.vfp_regs[regno - ARM_D0_RE= GNUM]); >>>>> } >>>>> + else >>>>> + warning (_("Invalid register number.")); >>>>> >>>>> ret =3D ptrace (PT_SETFPREGS, regcache->ptid ().pid (), >>>>> (PTRACE_TYPE_ARG3) &inferior_fp_registers, 0); >>>>> @@ -361,20 +352,17 @@ store_fp_register (const struct regcache *regca= che, int regno) >>>>> static void >>>>> store_fp_regs (const struct regcache *regcache) >>>>> { >>>>> - struct fpreg inferior_fp_registers; >>>>> - int ret; >>>>> - int regno; >>>>> + struct fpreg fpregs; >>>>> >>>>> - >>>>> - for (regno =3D ARM_F0_REGNUM; regno <=3D ARM_F7_REGNUM; regno++) >>>>> + for (int regno =3D ARM_D0_REGNUM; regno <=3D ARM_D31_REGNUM; regno= ++) >>>>> regcache->raw_collect >>>>> - (regno, (char *) &inferior_fp_registers.fpr[regno - ARM_F0_REG= NUM]); >>>>> + (regno, (char *) &fpregs.fpr_vfp.vfp_regs[regno - ARM_D0_REGNU= M]); >>>>> >>>>> - regcache->raw_collect (ARM_FPS_REGNUM, >>>>> - (char *) &inferior_fp_registers.fpr_fpsr); >>>>> + regcache->raw_collect (ARM_FPSCR_REGNUM, >>>>> + (char *) &fpregs.fpr_vfp.vfp_fpscr); >>>>> >>>>> - ret =3D ptrace (PT_SETFPREGS, regcache->ptid ().pid (), >>>>> - (PTRACE_TYPE_ARG3) &inferior_fp_registers, 0); >>>>> + int ret =3D ptrace (PT_SETFPREGS, regcache->ptid ().pid (), >>>>> + (PTRACE_TYPE_ARG3) &fpregs, 0); >>>>> >>>>> if (ret < 0) >>>>> warning (_("unable to store floating-point registers")); >>>>> @@ -427,7 +415,7 @@ fetch_elfcore_registers (struct regcache *regcach= e, >>>>> /* The memcpy may be unnecessary, but we can't really be sure >>>>> of the alignment of the data in the core file. */ >>>>> memcpy (&fparegset, core_reg_sect, sizeof (fparegset)); >>>>> - arm_supply_fparegset (regcache, &fparegset); >>>>> + arm_supply_vfpregset (regcache, &fparegset); >>>>> } >>>>> break; >>>>> >>>>> -- >>>>> 2.25.0.225.g125e21ebc7-goog >>>>> >>> >=20 >=20 --RZd6ecHIKiua8sMM87pmAURIgg3h0tqTH-- --ABNQBP227S4cCLG4CwaBDumL0xGArRPHb Content-Type: application/pgp-signature; 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