From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 113313 invoked by alias); 18 Oct 2017 20:15:43 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 112794 invoked by uid 89); 18 Oct 2017 20:15:42 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_SPAM,RP_MATCHES_RCVD,SPF_PASS autolearn=no version=3.3.2 spammy=H*MI:google, H*M:google X-HELO: mail-qk0-f202.google.com Received: from mail-qk0-f202.google.com (HELO mail-qk0-f202.google.com) (209.85.220.202) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 18 Oct 2017 20:15:41 +0000 Received: by mail-qk0-f202.google.com with SMTP id b62so7120393qkh.18 for ; Wed, 18 Oct 2017 13:15:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:message-id:date:subject:from:to:cc; bh=CSFnfSWF/klN5bi1uXEgi9Xwjlrj1ut4qnwFTAh9rT0=; b=rg5Brd1u9/Wzf0G3NLtyMUk5x4yA1EfSJ0TxPxEu8jCvjzo+3iLDWEceYVDctdmndC oBkUsijGPiXI87JjtJY5uQ2jsZUneXzPPO940qYTKYdoBuixqC4w46Fsi8xSbJ/q8AkD igklDwO19WpKBHnHBj0iH8FZfycgwL1jzhKypn/JBzMrjl1L8pQDv9vtLclXGR683cO1 iQcjASclAkvigXSCMXpKKlnSeM5HcVO8EiSOs4mfHQ8Wqgl+5YiTXrdNWghSLuIfMSxP vFDySpbjHK010quGl0cMUsKZCMiPcA2vepthXAt+PTQVLERn4Nr1gbh3GlEaR1X2s5Kc U9Kg== X-Gm-Message-State: AMCzsaXfe7iEAwjgLng+vjUO4lJgtAqpCfvRkMTJZcP72ObVPUdrmdIV D6+1hmo5JzVUT5avEgcOa/TuPoA= X-Google-Smtp-Source: AOwi7QCt/liL+GD9dk15S0mfVupN1RL3g/WM4kVwM2d3wAVAeqlQ8VQ37iw5vBN+0aHAPwogILrBIps= MIME-Version: 1.0 X-Received: by 10.55.100.85 with SMTP id y82mr13170440qkb.19.1508357735730; Wed, 18 Oct 2017 13:15:35 -0700 (PDT) Message-ID: <94eb2c05879608d374055bd7e7c3@google.com> Date: Wed, 18 Oct 2017 20:15:00 -0000 Subject: Re: [PATCH v6 3/6] sim: or1k: add or1k target to sim From: "Doug Evans via gdb-patches" Reply-To: Doug Evans To: Stafford Horne Cc: GDB patches , Simon Marchi , Mike Frysinger , Openrisc Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2017-10/txt/msg00576.txt.bz2 Stafford Horne writes: > This adds the OpenRISC 32-bit sim target. The OpenRISC sim is a CGEN > based sim so the bulk of the code is generated from the .cpu files by > CGEN. The engine decode and execute logic in mloop uses scache with > pseudo-basic-block extraction and supports both full and fast (switch) > modes. > > The sim does not implement an mmu at the moment. The sim does implement > fpu instructions via the common sim-fpu implementation. > > sim/ChangeLog: > > 2017-09-13 Stafford Horne > Peter Gavin > > * configure.tgt: Add or1k sim. > * or1k/README: New file. > * or1k/Makefile.in: New file. > * or1k/configure.ac: New file. > * or1k/mloop.in: New file. > * or1k/or1k-sim.h: New file. > * or1k/or1k.c: New file. > * or1k/sim-if.c: New file. > * or1k/sim-main.h: New file. > * or1k/traps.c: New file. LGTM