From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15681 invoked by alias); 10 Sep 2012 10:21:53 -0000 Received: (qmail 15673 invoked by uid 22791); 10 Sep 2012 10:21:52 -0000 X-SWARE-Spam-Status: No, hits=-6.3 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,RCVD_IN_DNSWL_HI,RCVD_IN_HOSTKARMA_W,RP_MATCHES_RCVD,SPF_HELO_PASS X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 10 Sep 2012 10:21:35 +0000 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q8AALYgT026512 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Mon, 10 Sep 2012 06:21:34 -0400 Received: from Cadeux.redhat.com (vpn1-5-56.ams2.redhat.com [10.36.5.56]) by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id q8AALVag007165 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES128-SHA bits=128 verify=NO); Mon, 10 Sep 2012 06:21:33 -0400 From: Nick Clifton To: dj@redhat.com Cc: gdb-patches@sourceware.org Subject: RFA: V850 sim: various fixes. Date: Mon, 10 Sep 2012 10:21:00 -0000 Message-ID: <87zk4yxjyr.fsf@redhat.com> MIME-Version: 1.0 Content-Type: text/plain Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2012-09/txt/msg00104.txt.bz2 Hi DJ, The patch below fixes a variety of small bugs in the V850 simulator's igen file. It also adds a snippet of code to catch attempts to execute code via a NULL pointer. With these changes applied I am seeing much better gcc testsuite results for the v850 toolchain, especially when checking the e2v3 multilib. OK to apply ? Cheers Nick sim/v850/ChangeLog 2012-09-10 Nick Clifton * v850.igen (W,WWWW): Correct computation of register number. (JR32): Remove unnecessary comma. (nop): Add trap when executing code at address 0. (cmovf.s): Register 0 is an invalid source register. (maddf.s): Remove bogus intermediary rounding. (nmaddf.s): Likewise. (trncf.sl): Remove bogus initial rounding. (trncf.dw): Likewise. (trncf.sl): Likewise. (trncf.sw): Likewise. Index: sim/v850/v850.igen =================================================================== RCS file: /cvs/src/src/sim/v850/v850.igen,v retrieving revision 1.10 diff -u -3 -p -r1.10 v850.igen --- sim/v850/v850.igen 29 Mar 2012 00:57:19 -0000 1.10 +++ sim/v850/v850.igen 10 Sep 2012 10:12:45 -0000 @@ -25,7 +25,7 @@ :cache:::unsigned:reg1:RRRRR:(RRRRR) :cache:::unsigned:reg2:rrrrr:(rrrrr) :cache:::unsigned:reg3:wwwww:(wwwww) -:cache:::unsigned:reg4:W,WWWW:((W << 4) + WWWW) +:cache:::unsigned:reg4:W,WWWW:(W + (WWWW << 1)) :cache:::unsigned:reg1e:RRRR:(RRRR << 1) :cache:::unsigned:reg2e:rrrr:(rrrr << 1) @@ -773,7 +773,7 @@ rrrrr!0,11110,dddddd + ddddddddddddddd,0 // JR32 -00000010111,00000 + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jr32 +0000001011100000 + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jr32 *v850e2 *v850e2v3 "jr " @@ -1280,7 +1280,10 @@ rrrrr,111111,iiiii + wwwww,01001,IIII,10 0000000000000000:I:::nop "nop" { - /* do nothing, trace nothing */ + /* Catch indirection via a NULL pointer. + Memory from 0 - 0x10000 is filled with NOP instructions... */ + if (cia == 0) + sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); } @@ -2345,7 +2348,7 @@ rrrr,0111111,RRRR,0 + wwww!0,01000001,bb } // CMOVF.S -rrrrr,111111,RRRRR + wwwww!0,1000000,bbb,0:F_I:::cmovf_s +rrrrr,111111,RRRRR!0 + wwwww!0,1000000,bbb,0:F_I:::cmovf_s *v850e2v3 "cmovf.d , r, r, r" { @@ -2676,7 +2679,6 @@ rrrrr,111111,RRRRR + wwwww,101,W,00,WWWW TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3); status = sim_fpu_mul (&ans, &wop1, &wop2); - status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); wop1 = ans; status |= sim_fpu_add (&ans, &wop1, &wop3); status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); @@ -2954,7 +2956,6 @@ rrrrr,111111,RRRRR + wwwww,101,W,10,WWWW TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3); status = sim_fpu_mul (&ans, &wop1, &wop2); - status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); wop1 = ans; status |= sim_fpu_add (&ans, &wop1, &wop3); status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact); @@ -3190,8 +3191,7 @@ rrrr,011111100001 + wwww,010001010100:F_ sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); TRACE_FP_INPUT_FPU1 (&wop); - status = sim_fpu_round_64 (&wop, sim_fpu_round_zero, sim_fpu_denorm_zero); - status |= sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero); + status = sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero); check_cvt_fi(sd, status, 1); @@ -3212,8 +3212,7 @@ rrrr,011111100001 + wwwww,10001010000:F_ sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]); TRACE_FP_INPUT_FPU1 (&wop); - status = sim_fpu_round_32 (&wop, sim_fpu_round_zero, sim_fpu_denorm_zero); - status |= sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero); + status = sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero); check_cvt_fi(sd, status, 1); @@ -3233,8 +3232,7 @@ rrrrr,11111100001 + wwww,010001000100:F_ sim_fpu_32to (&wop, GR[reg2]); TRACE_FP_INPUT_FPU1 (&wop); - status = sim_fpu_round_64 (&wop, sim_fpu_round_zero, sim_fpu_denorm_zero); - status |= sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero); + status = sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero); GR[reg3e] = ans; GR[reg3e+1] = ans >> 32L; @@ -3253,12 +3251,10 @@ rrrrr,11111100001 + wwwww,10001000000:F_ sim_fpu_32to (&wop, GR[reg2]); TRACE_FP_INPUT_FPU1 (&wop); - status = sim_fpu_round_32 (&wop, sim_fpu_round_zero, sim_fpu_denorm_zero); - status |= sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero); + status = sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero); check_cvt_fi(sd, status, 0); GR[reg3] = ans; TRACE_FP_RESULT_WORD1 (ans); } -