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Thu, 10 Sep 2026 15:32:04 -0700 (PDT) Received: from localhost ([2804:14d:7e39:8083:f04c:42e3:5943:38f6]) by smtp.gmail.com with ESMTPSA id ada2fe7eead31-79278f87c8esm1048217137.1.2026.09.10.15.32.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2026 15:32:04 -0700 (PDT) From: Thiago Jung Bauermann To: Cc: , , , , , , Subject: Re: [PATCH v4 1/5] gdb/aarch64: Add POR_EL0 register support for FEAT_S1POE In-Reply-To: <87bja5pp2r.fsf@linaro.org> (Thiago Jung Bauermann's message of "Thu, 10 Sep 2026 07:01:32 +0000") References: <20260901091216.5711-1-srinath.parvathaneni@arm.com> <20260901091216.5711-2-srinath.parvathaneni@arm.com> <87bja5pp2r.fsf@linaro.org> User-Agent: mu4e 1.14.3; emacs 30.2 Date: Thu, 10 Sep 2026 22:32:01 +0000 Message-ID: <87tsnwohzy.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org Thiago Jung Bauermann writes: > writes: > >> Add support for the FEAT_S1POE POR_EL0 register on AArch64. >> >> This patch adds POR_EL0 to the AArch64 register set and reads/writes it >> using the NT_ARM_POE ptrace regset. >> >> It also adds POE pseudo-registers por_p0 through por_p15, with each >> pseudo-register mapping to a 4-bit field in POR_EL0, starting from the >> least-significant nibble. >> >> POR_EL0 and the POE pseudo-registers are added to the "por" register >> group, allowing them to be displayed together using the >> "info registers por" command. >> >> With this change, POR_EL0 is accessible through: >> >> * info registers >> * info registers por_el0 >> * info registers por >> * p $por_el0 >> * p/x $por_el0 >> * set $por_el0 =3D >> >> The individual POE fields can also be accessed and modified through >> $por_p0 to $por_p15. >> >> Example: >> (gdb) info register por_el0 >> por_el0 0x7 [ P0=3Drwx ] >> (gdb) set $por_el0=3D0xffffffff77777777 >> (gdb) info registers por_el0 >> por_el0 0xffffffff77777777 [ P15=3D??? P14=3D??? P13=3D??? P12=3D= ??? >> P11=3D??? P10=3D??? P9=3D??? P8=3D??? >> P7=3Drwx P6=3Drwx P5=3Drwx P4=3Drwx >> P3=3Drwx P2=3Drwx P1=3Drwx P0=3Drwx ] >> (gdb) info registers por >> por_el0 0xffffffff77777777 [ P15=3D??? P14=3D??? P13=3D??? P12=3D= ??? >> P11=3D??? P10=3D??? P9=3D??? P8=3D??? >> P7=3Drwx P6=3Drwx P5=3Drwx P4=3Drwx >> P3=3Drwx P2=3Drwx P1=3Drwx P0=3Drwx ] >> por_p0 0x7 rwx >> por_p1 0x7 rwx >> por_p2 0x7 rwx >> por_p3 0x7 rwx >> por_p4 0x7 rwx >> por_p5 0x7 rwx >> por_p6 0x7 rwx >> por_p7 0x7 rwx >> por_p8 0xf ??? >> por_p9 0xf ??? >> por_p10 0xf ??? >> por_p11 0xf ??? >> por_p12 0xf ??? >> por_p13 0xf ??? >> por_p14 0xf ??? >> por_p15 0xf ??? >> >> Individual POE pseudo-registers can be written independently, with the >> corresponding 4-bit field in POR_EL0 updated accordingly. For example: >> >> (gdb) set $por_el0=3D0x7 >> (gdb) info registers por_el0 >> por_el0 0x0000000000000007 [ P0=3Drwx ] >> (gdb) set $por_p1=3D0x7 >> (gdb) info registers por_el0 >> por_el0 0x0000000000000077 [ P1=3Drwx P0=3Drwx ] > > I like this output and the pseudo registers. Thanks! One more thing that I remembered today: Considering that the print command doesn't show the "pretty" output: (gdb) p $por_el0 $1 =3D 21474836487 (gdb) p/x $por_el0 $2 =3D 0x500000007 (gdb) p $por_p8 $3 =3D 5 It would be useful to add a new "Permission Overlay Extension" section in the GDB manual (under Configurations =E2=86=92 Architectures =E2=86=92 A= Arch64) mentioning the use of the "info registers" command to get the fancier output, the poe register group and setting/getting individual fields with the pseudo-registers. --=20 Thiago (he/him)