[PATCH v2 2/4] arc: Recognize registers available on Linux targets

Shahab Vahedi
2020-04-28T16:04:58Z

From: Anton Kolesov <Anton.Kolesov@synopsys.com>

For ARC there are registers that are not part of a required set in XML target
descriptions by default, but which are almost always present on ARC targets and
are universally exposed by the ptrace interface. This patch adds those
registers to those recognized by GDB:

- R30 - core register available in user-space on ARC HS processors only (used
to be a privileged only ILINK2 on ARC700).
- R58, R59 - accumulator register pair for a 64-multiplier and
double-precision FPU - only on ARC HS.
- LP_START, LP_END - AUX registers, hardware loop start and end. Formally
optional, though it is hard to find ARC configuration that doesn't have
them and is always present in processors that can run Linux. GDB needs to
know about those registers to implement proper software single stepping,
since they affect what instruction will be next.
- BTA - AUX register that contains branch target address. Value of this
register makes sense only when execution halts at the delay slot
instruction - in this case branch instruction is already committed,
STATUS32.DE is set to 1 and BTA contains address of next PC. GDB needs to
understand this register to properly handle situations when breakpoint has
been set in the delay slot (delay slot is stepped over when doing software
single stepping). Unfortunately, right now this doesn't work very well,
because Linux doesn't allow modifications of STATUS32 via ptrace and Linux
uses TRAP_S instruction to implement software breakpoints - this
instruction commits when executed, therefore when TRAP_S is set in the
delay slot and execution halts at it, PC is already advanced to BTA value
and STATUS32.DE is reset. BTA register will be more useful for debugger
after support for SWI instruction will be added to ARC Linux - this
breakpoint instruction doesn't commit, hence it doesn't change processor
state.

v2: Changes after Tom's remarks:
arc-tdep.c
- arc_tdesc_init(): Use "ARC_{R58,R59}_REGNUM" to index "core_regs[]".
- arc_gdbarch_init(): Use "xfree ()" instead of "XDELETE ()"
- arc_gdbarch_init(): return "nullptr" instead of "NULL".

gdb/ChangeLog:
2020-04-28 Anton Kolesov <anton.kolesov@synopsys.com>

* arc-tdep.c (core_v2_register_names): Fix names of R58 and R59.
(aux_minimal_register_names): Add LP_START, LP_END and BTA.
(arc_tdesc_init): Recognize those registers.
* arc-tdep.h (arc_regnum): Add R58, R59, LP_START, LP_END and BTA.
(gdbarch_tdep): New field has_hw_loops.

gdb/doc/ChangeLog:
2020-04-28 Anton Kolesov <anton.kolesov@synopsys.com>

* gdb.texinfo (Synopsys ARC): Document LP_START, LP_END and BTA.
---
gdb/arc-tdep.c | 77 +++++++++++++++++++++++++++++++++++----------
gdb/arc-tdep.h | 17 ++++++++--
gdb/doc/gdb.texinfo | 3 +-
3 files changed, 78 insertions(+), 19 deletions(-)

diff --git a/gdb/arc-tdep.c b/gdb/arc-tdep.c
index a4f3f44b4fb..878728bc62c 100644
--- a/gdb/arc-tdep.c
+++ b/gdb/arc-tdep.c
@@ -117,12 +117,12 @@ static const char *const core_v2_register_names[] = {
"r44", "r45", "r46", "r47",
"r48", "r49", "r50", "r51",
"r52", "r53", "r54", "r55",
- "r56", "r57", "accl", "acch",
- "lp_count", "reserved", "limm", "pcl",
+ "r56", "r57", "r58", "r59",
+ "lp_count", "reserved", "limm", "pcl"
};

static const char *const aux_minimal_register_names[] = {
- "pc", "status32",
+ "pc", "status32", "lp_start", "lp_end", "bta"
};

static const char *const core_arcompact_register_names[] = {
@@ -141,7 +141,7 @@ static const char *const core_arcompact_register_names[] = {
"r48", "r49", "r50", "r51",
"r52", "r53", "r54", "r55",
"r56", "r57", "r58", "r59",
- "lp_count", "reserved", "limm", "pcl",
+ "lp_count", "reserved", "limm", "pcl"
};

static char *arc_disassembler_options = NULL;
@@ -1724,7 +1724,7 @@ static const struct frame_base arc_normal_base = {

static bool
arc_tdesc_init (struct gdbarch_info info, const struct target_desc **tdesc,
- struct tdesc_arch_data **tdesc_data)
+ struct tdesc_arch_data **tdesc_data, struct gdbarch_tdep *tdep)
{
if (arc_debug)
debug_printf ("arc: Target description initialization.\n");
@@ -1858,17 +1858,44 @@ arc_tdesc_init (struct gdbarch_info info, const struct target_desc **tdesc,
|| (i >= ARC_R16_REGNUM && i <= ARC_R25_REGNUM)))
continue;

- valid_p = tdesc_numbered_register (feature, tdesc_data_loc, i,
- core_regs[i]);
+ /* R58 and R59 can have special names: ACCL and ACCH, however which
+ one is which depends on target endianness - for little endian R58
+ is ACCL, R59 is ACCH; vice versa for big endian. */
+
+ const char *const r58_names[] = {
+ core_regs[ARC_R58_REGNUM],
+ (info.byte_order == BFD_ENDIAN_LITTLE ? "accl" : "acch"),
+ NULL
+ };
+ const char *const r59_names[] = {
+ core_regs[ARC_R59_REGNUM],
+ (info.byte_order == BFD_ENDIAN_LITTLE ? "acch" : "accl"),
+ NULL
+ };
+
+ switch (i)
+ {
+ case ARC_R58_REGNUM:
+ valid_p = tdesc_numbered_register_choices (feature, tdesc_data_loc,
+ i, r58_names);
+ break;
+ case ARC_R59_REGNUM:
+ valid_p = tdesc_numbered_register_choices (feature, tdesc_data_loc,
+ i, r59_names);
+ break;
+ default:
+ valid_p = tdesc_numbered_register (feature, tdesc_data_loc, i,
+ core_regs[i]);
+ }

/* - Ignore errors in extension registers - they are optional.
- Ignore missing ILINK because it doesn't make sense for Linux.
- - Ignore missing ILINK2 when architecture is ARCompact, because it
- doesn't make sense for Linux targets.
+ - Ignore missing ILINK2 when architecture is ARCompact, because
+ it doesn't make sense for Linux targets.

- In theory those optional registers should be in separate features, but
- that would create numerous but tiny features, which looks like an
- overengineering of a rather simple task. */
+ In theory those optional registers should be in separate
+ features, but that would create numerous but tiny features, which
+ looks like an overengineering of a rather simple task. */
if (!valid_p && (i <= ARC_SP_REGNUM || i == ARC_BLINK_REGNUM
|| i == ARC_LP_COUNT_REGNUM || i == ARC_PCL_REGNUM
|| (i == ARC_R30_REGNUM && is_arcv2)))
@@ -1895,7 +1922,9 @@ arc_tdesc_init (struct gdbarch_info info, const struct target_desc **tdesc,
{
const char *name = aux_minimal_register_names[i - ARC_FIRST_AUX_REGNUM];
valid_p = tdesc_numbered_register (feature, tdesc_data_loc, i, name);
- if (!valid_p)
+
+ /* Only STATUS32 and PC are mandatory. */
+ if (!valid_p && (i == ARC_PC_REGNUM || i == ARC_STATUS32_REGNUM))
{
arc_print (_("Error: Cannot find required register `%s' "
"in feature `%s'.\n"),
@@ -1903,6 +1932,11 @@ arc_tdesc_init (struct gdbarch_info info, const struct target_desc **tdesc,
tdesc_data_cleanup (tdesc_data_loc);
return false;
}
+ /* Hardware loops present if both its registers are. */
+ else if (ARC_LP_START_REGNUM == i)
+ tdep->has_hw_loops = valid_p;
+ else if (ARC_LP_END_REGNUM == i)
+ tdep->has_hw_loops &= valid_p;
}

*tdesc = tdesc_loc;
@@ -1950,13 +1984,17 @@ arc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
if (arc_debug)
debug_printf ("arc: Architecture initialization.\n");

- if (!arc_tdesc_init (info, &tdesc, &tdesc_data))
- return NULL;
-
/* Allocate the ARC-private target-dependent information structure, and the
GDB target-independent information structure. */
struct gdbarch_tdep *tdep = XCNEW (struct gdbarch_tdep);
tdep->jb_pc = -1; /* No longjmp support by default. */
+
+ if (!arc_tdesc_init (info, &tdesc, &tdesc_data, tdep))
+ {
+ xfree (tdep);
+ return nullptr;
+ }
+
struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep);

/* Data types. */
@@ -1987,6 +2025,13 @@ arc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
set_gdbarch_ps_regnum (gdbarch, ARC_STATUS32_REGNUM);
set_gdbarch_fp0_regnum (gdbarch, -1); /* No FPU registers. */

+ /* Confirm that register name lists have proper length. */
+ gdb_static_assert (ARC_LAST_REGNUM + 1
+ == (ARRAY_SIZE (core_v2_register_names)
+ + ARRAY_SIZE (aux_minimal_register_names)));
+ gdb_static_assert (ARRAY_SIZE (core_v2_register_names)
+ == ARRAY_SIZE (core_arcompact_register_names));
+
set_gdbarch_push_dummy_call (gdbarch, arc_push_dummy_call);
set_gdbarch_push_dummy_code (gdbarch, arc_push_dummy_code);

diff --git a/gdb/arc-tdep.h b/gdb/arc-tdep.h
index d72332c7638..8fd8571457f 100644
--- a/gdb/arc-tdep.h
+++ b/gdb/arc-tdep.h
@@ -23,6 +23,7 @@

/* Need disassemble_info. */
#include "dis-asm.h"
+#include "gdbarch.h"
#include "arch/arc.h"

/* To simplify GDB code this enum assumes that internal regnums should be same
@@ -54,6 +55,8 @@ enum arc_regnum
ARC_R30_REGNUM,
/* Return address from function. */
ARC_BLINK_REGNUM,
+ ARC_R58_REGNUM = 58,
+ ARC_R59_REGNUM,
/* Zero-delay loop counter. */
ARC_LP_COUNT_REGNUM = 60,
/* Reserved register number. There should never be a register with such
@@ -69,14 +72,21 @@ enum arc_regnum
/* Program counter, aligned to 4-bytes, read-only. */
ARC_PCL_REGNUM,
ARC_LAST_CORE_REGNUM = ARC_PCL_REGNUM,
+
/* AUX registers. */
/* Actual program counter. */
ARC_PC_REGNUM,
ARC_FIRST_AUX_REGNUM = ARC_PC_REGNUM,
/* Status register. */
ARC_STATUS32_REGNUM,
- ARC_LAST_REGNUM = ARC_STATUS32_REGNUM,
- ARC_LAST_AUX_REGNUM = ARC_STATUS32_REGNUM,
+ /* Zero-delay loop start instruction. */
+ ARC_LP_START_REGNUM,
+ /* Zero-delay loop next-after-last instruction. */
+ ARC_LP_END_REGNUM,
+ /* Branch target address. */
+ ARC_BTA_REGNUM,
+ ARC_LAST_AUX_REGNUM = ARC_BTA_REGNUM,
+ ARC_LAST_REGNUM = ARC_LAST_AUX_REGNUM,

/* Additional ABI constants. */
ARC_FIRST_ARG_REGNUM = ARC_R0_REGNUM,
@@ -101,6 +111,9 @@ struct gdbarch_tdep
/* Offset to PC value in jump buffer. If this is negative, longjmp
support will be disabled. */
int jb_pc;
+
+ /* Whether target has hardware (aka zero-delay) loops. */
+ bool has_hw_loops;
};

/* Utility functions used by other ARC-specific modules. */
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index 385c832f222..1671d44c6c8 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -45115,7 +45115,8 @@ difference with @samp{org.gnu.gdb.arc.core.v2} feature is in the names of
ARC v2, but @samp{ilink2} is optional on ARCompact.

The @samp{org.gnu.gdb.arc.aux-minimal} feature is required for all ARC
-targets. It should contain registers @samp{pc} and @samp{status32}.
+targets. It should contain registers @samp{pc} and @samp{status32}. It may
+contain registers @samp{lp_start}, @samp{lp_end} and @samp{bta}.

@node ARM Features
@subsection ARM Features
--
2.26.2