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[87.115.72.15]) by smtp.gmail.com with ESMTPSA id k5-20020a05600c1c8500b003a2e5f536b3sm20448077wms.24.2022.08.09.04.05.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Aug 2022 04:05:32 -0700 (PDT) To: Mark Goncharov , gdb-patches@sourceware.org Subject: Re: [PATCH] [gdb/riscv] Fix test for riscv: zero register. In-Reply-To: <20220808130147.2715849-1-mark.goncharov@syntacore.com> References: <20220808130147.2715849-1-mark.goncharov@syntacore.com> Date: Tue, 09 Aug 2022 12:05:31 +0100 Message-ID: <87a68d1xtw.fsf@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Andrew Burgess via Gdb-patches Reply-To: Andrew Burgess Cc: mga-sc Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" Mark Goncharov writes: > From: mga-sc > > x0 register in riscv must have permanent value. > We already have test for that: gdb/testsuite/riscv-reg-aliases.exp. > This patch fixes 4 test drops. Thanks for this. I guess you must be using a target that doesn't like it if GDB tries to write to x0? The native Linux target for example is fine with writes to x0, as the kernel already ignores these. It's always nice to include these sorts of details in the commit message. I also wanted to tweak some of the comments, there's an updated patch below, are you happy if I push this? I've kept the text about the target generic, but if you have any additional details I'd be happy to add these before committing. Thanks, Andrew --- commit e5b1b4690ba1bab285e5a4341990dcca43343b77 Author: mga-sc Date: Mon Aug 8 16:01:47 2022 +0300 gdb/riscv: implement cannot_store_register gdbarch method The x0 (zero) register is read-only on RISC-V. Implement the cannot_store_register gdbarch method to tell GDB this. Without this method GDB will try to write to x0, and relies on the target to ignore such writes. If you are using a target that complains (or throws an error) when writing to x0, this change will prevent this from happening. The gdb.arch/riscv-reg-aliases.exp test exercises writing to x0, and will show the errors when using a suitable target. diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 2d41be96b20..b9a51f7ae6a 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -933,6 +933,15 @@ riscv_register_name (struct gdbarch *gdbarch, int regnum) return name; } +/* Implement the cannot_store_register gdbarch method. The zero register + (x0) is read-only on RISC-V. */ + +static int +riscv_cannot_store_register (struct gdbarch *gdbarch, int regnum) +{ + return regnum == RISCV_ZERO_REGNUM; +} + /* Construct a type for 64-bit FP registers. */ static struct type * @@ -3822,6 +3831,9 @@ riscv_gdbarch_init (struct gdbarch_info info, registers, no matter what the target description called them. */ set_gdbarch_register_name (gdbarch, riscv_register_name); + /* Tell GDB which RISC-V registers are read-only. */ + set_gdbarch_cannot_store_register (gdbarch, riscv_cannot_store_register); + /* Override the register group callback setup by the target description mechanism. This allows us to force registers into the groups we want, ignoring what the target tells us. */