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Tue, 30 Jun 2026 22:16:23 -0700 (PDT) Received: from localhost ([2804:14d:7e39:8083:f04c:42e3:5943:38f6]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30ee2ffdbfesm15296687eec.11.2026.06.30.22.16.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jun 2026 22:16:23 -0700 (PDT) From: Thiago Jung Bauermann To: Srinath Parvathaneni Cc: "gdb-patches@sourceware.org" , "luis.machado.foss@gmail.com" , "guinevere@redhat.com" , Ezra Sitorus , Matthieu Longo , Mark Rutland , "maz@kernel.org" Subject: Re: [PATCH v2 1/7] gdb/aarch64: Add POR_EL0 register support for FEAT_S1POE In-Reply-To: (Srinath Parvathaneni's message of "Mon, 29 Jun 2026 10:44:27 +0000") References: <20260626180821.376406-1-srinath.parvathaneni@arm.com> <20260626180821.376406-2-srinath.parvathaneni@arm.com> <87a4sgikk4.fsf@linaro.org> User-Agent: mu4e 1.14.2; emacs 30.2 Date: Wed, 01 Jul 2026 05:16:21 +0000 Message-ID: <874iijguhm.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org Hello Srinath, Srinath Parvathaneni writes: >>> * info registers por_el0 >>> * p $por_el0 >>> * p/x $por_el0 >>> * set $por_el0 = >> >>One question, more about general policy on the AArch64 GDB port: >> >>Should the register name have the _el0 suffix? It's more than half of >>the register name (though tab completion helps). >> >>We don't currently have that suffix in the name of any register. And in >>the case of Guarded Control Stack, I didn't add it. For native >>debugging, it will always be the register at EL0. For remote debugging, >>I assumed the target would send the register corresponding to the >>current exception level in the inferior. >> >>Can there be a situation where it would be possible to see both the EL0 >>and EL1 (for example) registers at the same time? Or a situation where >>the inferior is at EL1 but one wants to see the register at EL0, or >>vice-versa? >> > > Thanks Thiago for the review. I'll address the other review comments and > post a new version of the patches. > > I'm happy to follow the existing AArch64 GDB convention and expose the register > as `POR` for consistency. > > That said, after discussing this with kernel/KVM developers, there are valid > debugging scenarios (e.g. KGDB or guest debugging via KVM/QEMU) where exposing > `POR_EL0`, `POR_EL1`, and `POR_EL2` simultaneously would be useful. Thanks for checking! Considering it's indeed useful then it's better to use $por_el0 in this patch series as you have done. > This seems like a broader GDB register naming issue rather than > something specific to FEAT_S1POE. I agree. This just seemed like a good moment to consider this question. -- Thiago (he/him)