From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 10412 invoked by alias); 23 Nov 2009 19:36:23 -0000 Received: (qmail 10403 invoked by uid 22791); 23 Nov 2009 19:36:22 -0000 X-SWARE-Spam-Status: No, hits=-0.1 required=5.0 tests=BAYES_00,RCVD_ILLEGAL_IP,SPF_SOFTFAIL X-Spam-Check-By: sourceware.org Received: from cdptpa-omtalb.mail.rr.com (HELO cdptpa-omtalb.mail.rr.com) (75.180.132.122) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 23 Nov 2009 19:36:16 +0000 Received: from sk22g2 ([71.70.78.104]) by cdptpa-omta02.mail.rr.com with ESMTP id <20091123193614036.TPFX27026@cdptpa-omta02.mail.rr.com> for ; Mon, 23 Nov 2009 19:36:14 +0000 Received: from sk22g2.localdomain.ysato.dip.jp (sk22g2.localdomain [127.0.1.1]) by sk22g2 (Postfix) with ESMTP id BAE90C1F for ; Mon, 23 Nov 2009 14:36:13 -0500 (EST) Date: Mon, 23 Nov 2009 19:36:00 -0000 Message-ID: <873a45rq36.wl%ysato@users.sourceforge.jp> From: Yoshinori Sato To: gdb-patches Subject: [PATCH] sim/h8300 different result some addressing User-Agent: Wanderlust/2.15.6 (Almost Unreal) SEMI/1.14.6 (Maruoka) FLIM/1.14.9 (=?ISO-2022-JP-2?B?R29qGyQoRCtXGyhC?=) APEL/10.7 Emacs/23.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Content-Type: text/plain; charset=US-ASCII X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2009-11/txt/msg00503.txt.bz2 Test code .h8300h mov.l #0x12345678,er0 mov.w #0xabcd,r1 mov.w r1,@-er0 Real CPU result mem 0x345676 -> 0xabcd reg er0 -> 0x12345676 Sim result mem 0x345676 -> 0xabcd reg er0 -> 0x00345676 Sim broke er0 value. Index: sim/h8300/ChangeLog =================================================================== RCS file: /cvs/src/src/sim/h8300/ChangeLog,v retrieving revision 1.63 diff -u -r1.63 ChangeLog --- sim/h8300/ChangeLog 22 Aug 2009 16:56:53 -0000 1.63 +++ sim/h8300/ChangeLog 23 Nov 2009 19:17:06 -0000 @@ -1,3 +1,9 @@ +2009-11-23 Yoshinori Sato + * compile.c(fetch_1): Fix pre-dec, pre-inc, post-dec and post-inc. + Index registers not masked memory areas. + Only simply increment or decrement. + * compile.c(store_1): Ditto. + 2009-08-22 Ralf Wildenhues * config.in: Regenerate. Index: sim/h8300/compile.c =================================================================== RCS file: /cvs/src/src/sim/h8300/compile.c,v retrieving revision 1.45 diff -u -r1.45 compile.c --- sim/h8300/compile.c 1 Dec 2008 16:10:45 -0000 1.45 +++ sim/h8300/compile.c 23 Nov 2009 19:17:08 -0000 @@ -1386,105 +1386,93 @@ break; case X (OP_POSTINC, SB): /* Register indirect w/post-incr: byte. */ t = GET_L_REG (rn); - t &= h8_get_mask (sd); - r = GET_MEMORY_B (t); + r = GET_MEMORY_B (t & h8_get_mask (sd)); if (!twice) t += 1; - t = t & h8_get_mask (sd); SET_L_REG (rn, t); *val = r; break; case X (OP_POSTINC, SW): /* Register indirect w/post-incr: word. */ t = GET_L_REG (rn); - t &= h8_get_mask (sd); - r = GET_MEMORY_W (t); + r = GET_MEMORY_W (t & h8_get_mask (sd)); if (!twice) t += 2; - t = t & h8_get_mask (sd); SET_L_REG (rn, t); *val = r; break; case X (OP_POSTINC, SL): /* Register indirect w/post-incr: long. */ t = GET_L_REG (rn); - t &= h8_get_mask (sd); - r = GET_MEMORY_L (t); + r = GET_MEMORY_L (t & h8_get_mask (sd)); if (!twice) t += 4; - t = t & h8_get_mask (sd); SET_L_REG (rn, t); *val = r; break; case X (OP_POSTDEC, SB): /* Register indirect w/post-decr: byte. */ t = GET_L_REG (rn); - t &= h8_get_mask (sd); - r = GET_MEMORY_B (t); + r = GET_MEMORY_B (t & h8_get_mask (sd)); if (!twice) t -= 1; - t = t & h8_get_mask (sd); SET_L_REG (rn, t); *val = r; break; case X (OP_POSTDEC, SW): /* Register indirect w/post-decr: word. */ t = GET_L_REG (rn); - t &= h8_get_mask (sd); - r = GET_MEMORY_W (t); + r = GET_MEMORY_W (t & h8_get_mask (sd)); if (!twice) t -= 2; - t = t & h8_get_mask (sd); SET_L_REG (rn, t); *val = r; break; case X (OP_POSTDEC, SL): /* Register indirect w/post-decr: long. */ t = GET_L_REG (rn); - t &= h8_get_mask (sd); - r = GET_MEMORY_L (t); + r = GET_MEMORY_L (t & h8_get_mask (sd)); if (!twice) t -= 4; - t = t & h8_get_mask (sd); SET_L_REG (rn, t); *val = r; break; case X (OP_PREDEC, SB): /* Register indirect w/pre-decr: byte. */ t = GET_L_REG (rn) - 1; - t &= h8_get_mask (sd); SET_L_REG (rn, t); + t &= h8_get_mask (sd); *val = GET_MEMORY_B (t); break; case X (OP_PREDEC, SW): /* Register indirect w/pre-decr: word. */ t = GET_L_REG (rn) - 2; - t &= h8_get_mask (sd); SET_L_REG (rn, t); + t &= h8_get_mask (sd); *val = GET_MEMORY_W (t); break; case X (OP_PREDEC, SL): /* Register indirect w/pre-decr: long. */ t = GET_L_REG (rn) - 4; - t &= h8_get_mask (sd); SET_L_REG (rn, t); + t &= h8_get_mask (sd); *val = GET_MEMORY_L (t); break; case X (OP_PREINC, SB): /* Register indirect w/pre-incr: byte. */ t = GET_L_REG (rn) + 1; - t &= h8_get_mask (sd); SET_L_REG (rn, t); + t &= h8_get_mask (sd); *val = GET_MEMORY_B (t); break; case X (OP_PREINC, SW): /* Register indirect w/pre-incr: long. */ t = GET_L_REG (rn) + 2; - t &= h8_get_mask (sd); SET_L_REG (rn, t); + t &= h8_get_mask (sd); *val = GET_MEMORY_W (t); break; case X (OP_PREINC, SL): /* Register indirect w/pre-incr: long. */ t = GET_L_REG (rn) + 4; - t &= h8_get_mask (sd); SET_L_REG (rn, t); + t &= h8_get_mask (sd); *val = GET_MEMORY_L (t); break; @@ -1621,8 +1609,8 @@ t = GET_L_REG (rn); if (!twice) t -= 1; - t &= h8_get_mask (sd); SET_L_REG (rn, t); + t &= h8_get_mask (sd); SET_MEMORY_B (t, n); break; @@ -1630,8 +1618,8 @@ t = GET_L_REG (rn); if (!twice) t -= 2; - t &= h8_get_mask (sd); SET_L_REG (rn, t); + t &= h8_get_mask (sd); SET_MEMORY_W (t, n); break; @@ -1639,8 +1627,8 @@ t = GET_L_REG (rn); if (!twice) t -= 4; - t &= h8_get_mask (sd); SET_L_REG (rn, t); + t &= h8_get_mask (sd); SET_MEMORY_L (t, n); break; @@ -1648,8 +1636,8 @@ t = GET_L_REG (rn); if (!twice) t += 1; - t &= h8_get_mask (sd); SET_L_REG (rn, t); + t &= h8_get_mask (sd); SET_MEMORY_B (t, n); break; @@ -1657,8 +1645,8 @@ t = GET_L_REG (rn); if (!twice) t += 2; - t &= h8_get_mask (sd); SET_L_REG (rn, t); + t &= h8_get_mask (sd); SET_MEMORY_W (t, n); break; @@ -1666,45 +1654,51 @@ t = GET_L_REG (rn); if (!twice) t += 4; - t &= h8_get_mask (sd); SET_L_REG (rn, t); + t &= h8_get_mask (sd); SET_MEMORY_L (t, n); break; case X (OP_POSTDEC, SB): /* Register indirect w/post-decr, byte. */ - t = GET_L_REG (rn) & h8_get_mask (sd); - SET_MEMORY_B (t, n); + t = GET_L_REG (rn); SET_L_REG (rn, t - 1); + t &= h8_get_mask (sd); + SET_MEMORY_B (t, n); break; case X (OP_POSTDEC, SW): /* Register indirect w/post-decr, word. */ - t = GET_L_REG (rn) & h8_get_mask (sd); - SET_MEMORY_W (t, n); + t = GET_L_REG (rn); SET_L_REG (rn, t - 2); + t &= h8_get_mask (sd); + SET_MEMORY_W (t, n); break; case X (OP_POSTDEC, SL): /* Register indirect w/post-decr, long. */ - t = GET_L_REG (rn) & h8_get_mask (sd); - SET_MEMORY_L (t, n); + t = GET_L_REG (rn); SET_L_REG (rn, t - 4); + t &= h8_get_mask (sd); + SET_MEMORY_L (t, n); break; case X (OP_POSTINC, SB): /* Register indirect w/post-incr, byte. */ - t = GET_L_REG (rn) & h8_get_mask (sd); - SET_MEMORY_B (t, n); + t = GET_L_REG (rn); SET_L_REG (rn, t + 1); + t &= h8_get_mask (sd); + SET_MEMORY_B (t, n); break; case X (OP_POSTINC, SW): /* Register indirect w/post-incr, word. */ - t = GET_L_REG (rn) & h8_get_mask (sd); - SET_MEMORY_W (t, n); + t = GET_L_REG (rn); SET_L_REG (rn, t + 2); + t &= h8_get_mask (sd); + SET_MEMORY_W (t, n); break; case X (OP_POSTINC, SL): /* Register indirect w/post-incr, long. */ - t = GET_L_REG (rn) & h8_get_mask (sd); - SET_MEMORY_L (t, n); + t = GET_L_REG (rn); SET_L_REG (rn, t + 4); + t &= h8_get_mask (sd); + SET_MEMORY_L (t, n); break; case X (OP_DISP, SB): /* Register indirect w/displacement, byte. */ -- Yoshinori Sato