From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26738 invoked by alias); 26 Nov 2015 12:48:31 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 26706 invoked by uid 89); 26 Nov 2015 12:48:25 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-pa0-f47.google.com Received: from mail-pa0-f47.google.com (HELO mail-pa0-f47.google.com) (209.85.220.47) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Thu, 26 Nov 2015 12:48:24 +0000 Received: by pabfh17 with SMTP id fh17so88933484pab.0 for ; Thu, 26 Nov 2015 04:48:22 -0800 (PST) X-Received: by 10.67.4.202 with SMTP id cg10mr56501970pad.81.1448542102737; Thu, 26 Nov 2015 04:48:22 -0800 (PST) Received: from E107787-LIN (gcc1-power7.osuosl.org. [140.211.15.137]) by smtp.gmail.com with ESMTPSA id 71sm27471237pfj.28.2015.11.26.04.48.19 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Thu, 26 Nov 2015 04:48:21 -0800 (PST) From: Yao Qi To: Antoine Tremblay Cc: Subject: Re: [PATCH v3 08/10] Support software single step on ARM in GDBServer. References: <1448287968-12907-1-git-send-email-antoine.tremblay@ericsson.com> <1448287968-12907-9-git-send-email-antoine.tremblay@ericsson.com> Date: Thu, 26 Nov 2015 12:48:00 -0000 In-Reply-To: <1448287968-12907-9-git-send-email-antoine.tremblay@ericsson.com> (Antoine Tremblay's message of "Mon, 23 Nov 2015 09:12:46 -0500") Message-ID: <86ziy1vsdr.fsf@gmail.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2015-11/txt/msg00556.txt.bz2 Antoine Tremblay writes: > Limitations : > > GDBServer can't step over a sigreturn or rt_sigreturn syscall since this = would > require the DWARF information to identify the caller PC. This situation > only prints a warning for the moment. They are using frame not DWARF to identify the PC, however, it is not necessary. When GDB or GDBserver is doing software single step, it must be in the inner-most frame, so we can get the caller PC by examining the stack at a certain offset from SP (from regcache), like what are doing in arm_linux_sigreturn_init and arm_linux_rt_sigreturn_init, rather than replying frame unwinding. See my comments to arm_get_next_pcs_syscall_next= _pc. > + > +/* Wrapper over syscall_next_pc for use in get_next_pcs. */ > + > +CORE_ADDR > +arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self, CORE_AD= DR pc) > +{ > + struct arm_gdb_get_next_pcs *next_pcs =3D (struct arm_gdb_get_next_pcs= *) self; > + struct gdbarch_tdep *tdep; > + > + tdep =3D gdbarch_tdep (next_pcs->gdbarch); > + if (tdep->syscall_next_pc !=3D NULL) > + return tdep->syscall_next_pc (next_pcs->frame); > + > + return 0; > +} > + > +/* When PC is at a syscall instruction, return the PC of the next > + instruction to be executed. */ > +static CORE_ADDR > +get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self, CORE_ADDR p= c) > +{ > + CORE_ADDR return_addr =3D 0; > + int is_thumb =3D self->is_thumb; > + ULONGEST svc_number =3D 0; > + > + if (is_thumb) > + { > + svc_number =3D self->ops->collect_register_unsigned (self, 7); > + return_addr =3D pc + 2; > + } > + else > + { > + unsigned long this_instr =3D self->ops->read_memory_unsigned_integ= er > + ((CORE_ADDR) pc, 4, self->byte_order_for_code); > + > + unsigned long svc_operand =3D (0x00ffffff & this_instr); > + if (svc_operand) /* OABI. */ > + { > + svc_number =3D svc_operand - 0x900000; > + } > + else /* EABI. */ > + { > + svc_number =3D self->ops->collect_register_unsigned (self, 7); > + } > + > + return_addr =3D pc + 4; > + } > + > + /* Is this a sigreturn or rt_sigreturn syscall? > + If so it is currently not handeled. */ > + if (svc_number =3D=3D 119 || svc_number =3D=3D 173) > + { > + if (debug_threads) > + debug_printf ("Unhandled sigreturn or rt_sigreturn syscall\n"); We can still compute the caller pc by examining stack. > + } > + > + /* Addresses for calling Thumb functions have the bit 0 set. */ > + if (is_thumb) > + return_addr =3D MAKE_THUMB_ADDR (return_addr); > + > + return return_addr; > +} >=20=20 This leads me thinking more about current software single step code in GDB. In GDB side, we are using frame to access registers, while in GDBserver, we are using regcache. Why don't we use regcache in both sides? so that the "struct arm_get_next_pcs_ops" can be simplified, for example, field collect_register_unsigned may be no longer necessary. In fact, software_single_step used to have regcache argument, added by https://sourceware.org/ml/gdb-patches/2007-04/msg00218.html but we changed to argument frame https://sourceware.org/ml/gdb-patches/2007-04/msg00218.html IMO, it is better to use regcache than frame. We have two options, #1, switch from frame apis to regcache apis to access registers in arm software single step. We can get regcache by get_current_regcache (). #2, change argument of gdbarch method software_single_step from frame to regcache, which means all its implementations need update, and switch to regcache apis to access registers. #2 is the right way to go in long term, and we really need to improve software_single_step. Let me what do you think. --=20 Yao (=E9=BD=90=E5=B0=A7)