From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 110112 invoked by alias); 9 May 2017 14:15:52 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 110029 invoked by uid 89); 9 May 2017 14:15:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-6.4 required=5.0 tests=BAYES_00,FREEMAIL_FROM,GIT_PATCH_1,RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_SPAM,SPF_PASS autolearn=ham version=3.3.2 spammy=sim, nios, Embedded, advised X-HELO: mail-wr0-f194.google.com Received: from mail-wr0-f194.google.com (HELO mail-wr0-f194.google.com) (209.85.128.194) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 09 May 2017 14:15:40 +0000 Received: by mail-wr0-f194.google.com with SMTP id v42so423812wrc.3 for ; Tue, 09 May 2017 07:15:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:references:date:in-reply-to :message-id:user-agent:mime-version:content-transfer-encoding; bh=Xzy127nwYVTHPtNorAjl0p7rs67nPnpbSm+980VMlZc=; b=VzajkpiJGKaBwRWq8naAoPKDXHT6lyjn7zyFWZKOLvP4uvZwRDw1LAnVSCdHlSROYm O/5jQ7RrU5H/sjdfJQ6EwYZg5ngwoNU/LzCTl4yx+Kis/20BnZjAF+eyRhAZWqMuljct wqfQrFKR6iuYCDV8IBsbI3aoQBX9nVrjxgzbXRutw4weEDYC+HnS3CCQ+lnFKesShyS1 jbp/ei89ZSy8EKvpaccTTqFqqFJ5UAhAd6wn86NLEWTurWqPlPOAYU5BQTGGS7tJ8B6V G6F0pLHiB3QuYVhTzkk6WzsGTGWeeCme9BhNSEVZT6bqI4qQJIABDwnkaBX1Fq+0w+/j yvCQ== X-Gm-Message-State: AODbwcDsHEZUi2qgNpLKdDvaTkUfgLVvj6tsIoi+Sk/MDZjHzNeHXTkP o9wQ+qU2qrMIbg== X-Received: by 10.223.138.139 with SMTP id y11mr232154wry.22.1494339340822; Tue, 09 May 2017 07:15:40 -0700 (PDT) Received: from E107787-LIN ([194.214.185.158]) by smtp.gmail.com with ESMTPSA id g25sm69236wra.1.2017.05.09.07.15.39 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Tue, 09 May 2017 07:15:40 -0700 (PDT) From: Yao Qi To: Stafford Horne Cc: GDB patches , Openrisc , Franck Jullien Subject: Re: [PATCH v6 2/5] gdb: Add OpenRISC or1k and or1knd target support References: <864lx38h2i.fsf@gmail.com> <20170502155305.GI2724@lianli.shorne-pla.net> Date: Tue, 09 May 2017 14:15:00 -0000 In-Reply-To: <20170502155305.GI2724@lianli.shorne-pla.net> (Stafford Horne's message of "Wed, 3 May 2017 00:53:05 +0900") Message-ID: <86shket8tx.fsf@gmail.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2017-05/txt/msg00212.txt.bz2 Stafford Horne writes: > I understand this is nothing new, but this tells to the users some extra > details about using target remote for OpenRISC (example which platforms > support it). Also, this is consistent with some other targets like > Microblaze. > All the targets listed in "Embedded Processors" do have "target remote". We don't have to document it for every one. IMO, we need to remove "target remote" from Microblaze part too. >> > + >> > +@kindex target sim >> > +@item target sim >> > + >> > +Runs the builtin CPU simulator which can run very basic >> > +programs but does not support most hardware functions like MMU. >> > +For more complex use cases the user is advised to run an external >> > +target, and connect using @samp{target remote}. >> > + >> > +Example: @code{target sim} >> > + >> > +@end table >> > + >> > @node PowerPC Embedded >> > @subsection PowerPC Embedded >> >=20=20 >> > @@ -41088,6 +41131,7 @@ registers using the capitalization used in >> > the description. >> > * M68K Features:: >> > * NDS32 Features:: >> > * Nios II Features:: >> > +* OpenRISC 1000 Features:: >> > * PowerPC Features:: >> > * S/390 and System z Features:: >> > * Sparc Features:: >> > @@ -41374,6 +41418,32 @@ targets. It should contain the 32 core >> > registers (@samp{zero}, >> > @samp{pc}, and the 16 control registers (@samp{status} through >> > @samp{mpuacc}). >> >=20=20 >> > +@node OpenRISC 1000 Features >> > +@subsection Openrisc 1000 Features >> > +@cindex target descriptions, OpenRISC 1000 features >> > + >> > +The @samp{org.gnu.gdb.or1k.group0} feature is required for OpenRISC 1= 000 >> > +targets. It should contain the 32 general purpose registers (@samp{r= 0} >> > +through @samp{r31}), @samp{ppc}, @samp{npc} and @samp{sr}. >> > + >> > +Along with the default reggroups like @samp{system} and @samp{general} >> > +provided by @value{GDBN}, OpenRISC targets can use the following regg= roups >> > +to group their many registers: >> > + >> > +@smallexample >> > + Group Type >> > + immu user >> > + dmmu user >> > + icache user >> > + dcache user >> > + pic user >> > + timer user >> > + power user >> > + perf user >> > + mac user >> > + debug user >> > +@end smallexample >> > + >>=20 >> Why do you need to document the reggroups? > > These register groups can be used by the target description features. If > not documented one would have to look into the code. In general arbitrary > groups are not allowed by features. This is also related to patch 1/5. "maintenance print reggroups" can tell the reggroups, so don't need to document them. --=20 Yao (=E9=BD=90=E5=B0=A7)