From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 11646 invoked by alias); 3 Dec 2015 11:17:20 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 11629 invoked by uid 89); 3 Dec 2015 11:17:19 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-pf0-f172.google.com Received: from mail-pf0-f172.google.com (HELO mail-pf0-f172.google.com) (209.85.192.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Thu, 03 Dec 2015 11:17:18 +0000 Received: by pfu207 with SMTP id 207so7533540pfu.2 for ; Thu, 03 Dec 2015 03:17:17 -0800 (PST) X-Received: by 10.98.13.25 with SMTP id v25mr12235984pfi.123.1449141437165; Thu, 03 Dec 2015 03:17:17 -0800 (PST) Received: from E107787-LIN (gcc1-power7.osuosl.org. [140.211.15.137]) by smtp.gmail.com with ESMTPSA id sy5sm10140495pac.5.2015.12.03.03.17.02 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Thu, 03 Dec 2015 03:17:15 -0800 (PST) From: Yao Qi To: Antoine Tremblay Cc: Subject: Re: [PATCH v4 4/6] Support software single step on ARM in GDBServer. References: <1449062264-18565-1-git-send-email-antoine.tremblay@ericsson.com> <1449062264-18565-5-git-send-email-antoine.tremblay@ericsson.com> Date: Thu, 03 Dec 2015 11:17:00 -0000 In-Reply-To: <1449062264-18565-5-git-send-email-antoine.tremblay@ericsson.com> (Antoine Tremblay's message of "Wed, 2 Dec 2015 08:17:42 -0500") Message-ID: <86a8pru6hf.fsf@gmail.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2015-12/txt/msg00040.txt.bz2 Antoine Tremblay writes: Some comments on the design, > +/* Context for a get_next_pcs call on ARM. */ > +struct arm_get_next_pcs > +{ > + /* Operations implementations. */ > + struct arm_get_next_pcs_ops *ops; > + /* Byte order for data. */ > + int byte_order; > + /* Byte order for code. */ > + int byte_order_for_code; > + /* Is the pc in thumb mode. */ > + int is_thumb; > + /* Use 32bit or 26 bit pc. */ > + int arm_apcs_32; > + /* Thumb2 breakpoint instruction. */ > + const gdb_byte *arm_thumb2_breakpoint; These fields are GDB specific, GDBserver doesn't need them at all. Can we move them to arm_gdb_get_next_pcs? Field is_thumb is used in both sides, but can't we compute it in two sides (through arm_is_thumb and arm_is_thumb_mode) respectively, rather than having a field here? > + /* Registry cache. */ > + struct regcache *regcache; > +}; > + > +/* get_next_pcs operations. */ > +struct arm_get_next_pcs_ops > +{ > + ULONGEST (*read_memory_unsigned_integer) (CORE_ADDR memaddr, > + int len, > + int byte_order); We need argument struct arm_get_next_pcs *self, and get rid of argument byte_order, which can be got through self. > + CORE_ADDR (*syscall_next_pc) (struct arm_get_next_pcs *self, CORE_ADDR= pc); > + CORE_ADDR (*addr_bits_remove) (struct arm_get_next_pcs *self, CORE_ADD= R val); > +}; > +/* Context for a get_next_pcs call on ARM in GDB. */ > +struct arm_gdb_get_next_pcs > +{ > + /* Common context for gdb/gdbserver. */ > + struct arm_get_next_pcs base; > + /* Frame information. */ > + struct frame_info *frame; FRAME is still used in arm_get_next_pcs_syscall_next_pc, but we should use regcache instead of frame there. Then we can remove frame here. > + /* Architecture dependent information. */ > + struct gdbarch *gdbarch; Is gdbarch used? > +}; --=20 Yao (=E9=BD=90=E5=B0=A7)