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[140.211.15.137]) by smtp.gmail.com with ESMTPSA id g27sm24442664pfd.47.2016.07.29.04.46.45 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 29 Jul 2016 04:46:48 -0700 (PDT) From: Yao Qi To: "Fredrik Hederstierna" Cc: gdb-patches@sourceware.org Subject: Re: [PATCH] Fix exception unwinding for ARM Cortex-M References: Date: Fri, 29 Jul 2016 11:47:00 -0000 In-Reply-To: (Fredrik Hederstierna's message of "Thu, 28 Jul 2016 08:13:06 +0000") Message-ID: <868twkekf1.fsf@gmail.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2016-07/txt/msg00371.txt.bz2 "Fredrik Hederstierna" writes: Fredrik, A general comment to this patch is that you need to split it. Each patch only addresses one issue or adds one support. > @@ -2919,15 +2966,47 @@ arm_m_exception_cache (struct frame_info *this_fr= ame) > cache->saved_regs[1].addr =3D unwound_sp + 4; > cache->saved_regs[2].addr =3D unwound_sp + 8; > cache->saved_regs[3].addr =3D unwound_sp + 12; > - cache->saved_regs[12].addr =3D unwound_sp + 16; > - cache->saved_regs[14].addr =3D unwound_sp + 20; > - cache->saved_regs[15].addr =3D unwound_sp + 24; > + cache->saved_regs[ARM_IP_REGNUM].addr =3D unwound_sp + 16; > + cache->saved_regs[ARM_LR_REGNUM].addr =3D unwound_sp + 20; > + cache->saved_regs[ARM_PC_REGNUM].addr =3D unwound_sp + 24; > cache->saved_regs[ARM_PS_REGNUM].addr =3D unwound_sp + 28; This change can be in a separate patch. Could you move it to separate patch, write changelog entry, and post it again? It is OK to commit. >=20=20 > + /* Check if extended stack frame (FPU regs stored) was used. */ > + extended_frame_used =3D ((lr & (1 << 4)) =3D=3D 0); > + if (extended_frame_used) > + { > + int i; > + int fpu_regs_stack_offset; > + > + /* This code does not take into account the lazy stacking, see "Lazy > + context save of FP state", in B1.5.7, also ARM AN298, supported > + by Cortex-M4F architecture. Give a warning and try do best effort. > + To fully handle this the FPCCR register (Floating-point Context > + Control Register) needs to be read out and the bits ASPEN and LSPEN > + could be checked to setup correct lazy stacked FP registers. */ > + > + warning (_("no FPU lazy stack unwinding supported, check FPCCR.")); > + > + fpu_regs_stack_offset =3D unwound_sp + 0x20; > + for (i =3D 0; i < 16; i++) > + { > + cache->saved_regs[ARM_D0_REGNUM + i].addr =3D fpu_regs_stack_offs= et; > + fpu_regs_stack_offset +=3D 4; > + } > + cache->saved_regs[ARM_FPSCR_REGNUM].addr =3D unwound_sp + 0x60; > + > + /* Offset 0x64 is reserved. */ > + cache->prev_sp =3D unwound_sp + 0x68; > + } > + else > + { > + /* Basic frame type used. */ > + cache->prev_sp =3D unwound_sp + 32; > + } > + I don't know much about lazy stacking, but it should be in a separate patch for lazy stacking. > /* If bit 9 of the saved xPSR is set, then there is a four-byte > aligner between the top of the 32-byte stack frame and the > previous context's stack pointer. */ > - cache->prev_sp =3D unwound_sp + 32; > if (safe_read_memory_integer (unwound_sp + 28, 4, byte_order, &xpsr) > && (xpsr & (1 << 9)) !=3D 0) > cache->prev_sp +=3D 4; > @@ -2977,6 +3056,41 @@ arm_m_exception_prev_register (struct frame_info *= this_frame, > prev_regnum); > } >=20=20 > +/* Determine if the program counter specified equals any of > + these magic return values defined by v7-M architecture. */ > + > +static int > +arm_m_pc_is_magic (CORE_ADDR pc) > +{ > + /* Exception frames return to one of these magic PCs defined in v7-M. > + For more details see "B1.5.8 Exception return behavior" > + in "ARMv7-M Architecture Reference Manual". */ We need to consider ARMv6-M as well, > + switch (pc) > + { > + /* From Table B1-8 and B1-9 the EXC_RETURN definition of > + the exception return behavior. */ > + > + /* Return to Handler mode. Return stack Main. Frame type Extended.= */ I don't see anything useful the comment has. We can remove it. Instead, we need to document, on ARMv6-M and ARMv7-M without FP extension, the exc_return is 0xfffffff{1,9,d}. On ARMv7-M with FP extension, exc_return can be 0xffffff{e,f}{1,9,d}. > + case 0xffffffe1: > + /* Return to Thread mode. Return stack Main. Frame type Extended. = */ > + case 0xffffffe9: > + /* Return to Thread mode. Return stack Process. Frame type Extende= d. */ > + case 0xffffffed: > + /* Return to Handler mode. Return stack Main. Frame type Basic. */ > + case 0xfffffff1: > + /* Return to Thread mode. Return stack Main. Frame type Basic. */ > + case 0xfffffff9: > + /* Return to Thread mode. Return stack Process. Frame type Basic. = */ > + case 0xfffffffd: > + /* PC is magic. */ > + return 1; > + > + default: > + /* PC is not magic. */ > + return 0; > + } > +} > + > /* Implementation of function hook 'sniffer' in > 'struct frame_uwnind'. */ >=20=20 > @@ -2990,14 +3104,8 @@ arm_m_exception_unwind_sniffer (const struct frame= _unwind *self, > /* No need to check is_m; this sniffer is only registered for > M-profile architectures. */ >=20=20 > - /* Exception frames return to one of these magic PCs. Other values > - are not defined as of v7-M. See details in "B1.5.8 Exception > - return behavior" in "ARMv7-M Architecture Reference Manual". */ > - if (this_pc =3D=3D 0xfffffff1 || this_pc =3D=3D 0xfffffff9 > - || this_pc =3D=3D 0xfffffffd) > - return 1; > - > - return 0; > + /* Check if exception frame returns to a magic PC value. */ > + return arm_m_pc_is_magic (this_pc); Please post the patch only for magic pc handling, then I can review and approve it. --=20 Yao (=E9=BD=90=E5=B0=A7)