From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 80037 invoked by alias); 2 May 2017 14:33:00 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 79985 invoked by uid 89); 2 May 2017 14:32:57 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-6.4 required=5.0 tests=BAYES_00,FREEMAIL_FROM,GIT_PATCH_1,RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_SPAM,SPF_PASS autolearn=ham version=3.3.2 spammy=stafford, Horne, horne, dmmu X-HELO: mail-wm0-f65.google.com Received: from mail-wm0-f65.google.com (HELO mail-wm0-f65.google.com) (74.125.82.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 02 May 2017 14:32:55 +0000 Received: by mail-wm0-f65.google.com with SMTP id y10so5065799wmh.0 for ; Tue, 02 May 2017 07:32:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:references:date:in-reply-to :message-id:user-agent:mime-version:content-transfer-encoding; bh=eHGvkWXixUoFLIBluZMowbc4grp2ONvpslaOnUoN0GA=; b=P1HMGH+qELVz9JUulFQplhrXka6FI6+SMGKKzpM+CBRqI2nZlZ9s/kJOiJ0jCNMmQr rc56dhRp7trhYzl1LKSaQ2V6TqyR26uVU2Clw9R/qTwxdsPFUGrSpwAse9QY5nMH0rbS jBSMYGZbx4H5ckVdLS/oaQla0bq3xyP0CE2DICRnLgO9xOVyVOS9Pce3pqhwv0cyLR2c Qn7m2fPgLXRIP5AjueRIFqJgr3ykWVFeu3Af9m4Qkhr1PTsYFzWHUFpl/PRD1r4+eWhl 3h7IbyipQ0rQBdo1DBGWdRGWSi0GoeMjz3kWzbPQc6MlcI5nexInaQbrJ6iox4lh5K37 FNsw== X-Gm-Message-State: AN3rC/7QrehOJDHWMSopy+haaUNkv56RM8A8ePDIBbtzAqC9B81GlQV6 MYSP+9UCkjSVxLAN X-Received: by 10.28.61.198 with SMTP id k189mr2259369wma.104.1493735575438; Tue, 02 May 2017 07:32:55 -0700 (PDT) Received: from E107787-LIN ([194.214.185.158]) by smtp.gmail.com with ESMTPSA id f63sm1313782wmh.8.2017.05.02.07.32.54 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Tue, 02 May 2017 07:32:54 -0700 (PDT) From: Yao Qi To: Stafford Horne Cc: GDB patches , Openrisc , Franck Jullien Subject: Re: [PATCH v6 2/5] gdb: Add OpenRISC or1k and or1knd target support References: Date: Tue, 02 May 2017 14:33:00 -0000 In-Reply-To: (Stafford Horne's message of "Mon, 24 Apr 2017 21:52:51 +0900") Message-ID: <864lx38h2i.fsf@gmail.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2017-05/txt/msg00007.txt.bz2 Stafford Horne writes: > +@kindex target remote > +@item target remote > + > +Connect to a remote OpenRISC 1000 target. This is supported by > +@dfn{Or1ksim}, the OpenRISC 1000 architectural simulator as well as QEMU, > +Verilator and Icarus Verilog simulators. @dfn{Remote serial protocol} > +servers, such as OpenOCD, are also available to drive various hardware > +implementations via JTAG. > + > +Example: @code{target remote :51000} Do we need to document "target remote"? which is not specific to any particular configurations. > + > +@kindex target sim > +@item target sim > + > +Runs the builtin CPU simulator which can run very basic > +programs but does not support most hardware functions like MMU. > +For more complex use cases the user is advised to run an external > +target, and connect using @samp{target remote}. > + > +Example: @code{target sim} > + > +@end table > + > @node PowerPC Embedded > @subsection PowerPC Embedded >=20=20 > @@ -41088,6 +41131,7 @@ registers using the capitalization used in the de= scription. > * M68K Features:: > * NDS32 Features:: > * Nios II Features:: > +* OpenRISC 1000 Features:: > * PowerPC Features:: > * S/390 and System z Features:: > * Sparc Features:: > @@ -41374,6 +41418,32 @@ targets. It should contain the 32 core register= s (@samp{zero}, > @samp{pc}, and the 16 control registers (@samp{status} through > @samp{mpuacc}). >=20=20 > +@node OpenRISC 1000 Features > +@subsection Openrisc 1000 Features > +@cindex target descriptions, OpenRISC 1000 features > + > +The @samp{org.gnu.gdb.or1k.group0} feature is required for OpenRISC 1000 > +targets. It should contain the 32 general purpose registers (@samp{r0} > +through @samp{r31}), @samp{ppc}, @samp{npc} and @samp{sr}. > + > +Along with the default reggroups like @samp{system} and @samp{general} > +provided by @value{GDBN}, OpenRISC targets can use the following reggrou= ps > +to group their many registers: > + > +@smallexample > + Group Type > + immu user > + dmmu user > + icache user > + dcache user > + pic user > + timer user > + power user > + perf user > + mac user > + debug user > +@end smallexample > + Why do you need to document the reggroups? > + > +extern initialize_file_ftype _initialize_or1k_tdep; /* -Wmissing-prototy= pes */ > + This is no longer needed, because GDB is moved to C++. Otherwise, the code is good to me. --=20 Yao (=E9=BD=90=E5=B0=A7)