From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 110332 invoked by alias); 11 Dec 2015 14:43:35 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 110275 invoked by uid 89); 11 Dec 2015 14:43:34 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-pf0-f169.google.com Received: from mail-pf0-f169.google.com (HELO mail-pf0-f169.google.com) (209.85.192.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Fri, 11 Dec 2015 14:43:33 +0000 Received: by pfnn128 with SMTP id n128so67187699pfn.0 for ; Fri, 11 Dec 2015 06:43:31 -0800 (PST) X-Received: by 10.98.67.207 with SMTP id l76mr15747741pfi.59.1449845010967; Fri, 11 Dec 2015 06:43:30 -0800 (PST) Received: from E107787-LIN (gcc1-power7.osuosl.org. [140.211.15.137]) by smtp.gmail.com with ESMTPSA id x86sm11216858pfi.68.2015.12.11.06.43.27 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 11 Dec 2015 06:43:29 -0800 (PST) From: Yao Qi To: Antoine Tremblay Cc: Subject: Re: [PATCH v7.1] Support software single step on ARM in GDBServer. References: <1449583641-18156-7-git-send-email-antoine.tremblay@ericsson.com> <1449691701-11845-1-git-send-email-antoine.tremblay@ericsson.com> Date: Fri, 11 Dec 2015 14:43:00 -0000 In-Reply-To: <1449691701-11845-1-git-send-email-antoine.tremblay@ericsson.com> (Antoine Tremblay's message of "Wed, 9 Dec 2015 15:08:21 -0500") Message-ID: <8637v9qc50.fsf@gmail.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2015-12/txt/msg00233.txt.bz2 Antoine Tremblay writes: > + /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction.= */ > + insn1 =3D self->ops->read_memory_unsigned_integer (loc, 2, byte_order_= for_code); > + > + loc +=3D 2; > + if (thumb_insn_size (insn1) !=3D 4) > + return NULL; > + > + insn2 =3D self->ops->read_memory_unsigned_integer (loc, 2, byte_order_= for_code); > + This line is too long, you may define a macro to shorten "self->ops->read_memory_unsigned_integer". > + loc +=3D 2; > + if (!((insn1 & 0xfff0) =3D=3D 0xe850 > + || ((insn1 & 0xfff0) =3D=3D 0xe8d0 && (insn2 & 0x00c0) =3D=3D 0x= 0040))) > + return NULL; > + > + /* Assume that no atomic sequence is longer than "atomic_sequence_leng= th" > + instructions. */ > + for (insn_count =3D 0; insn_count < atomic_sequence_length; ++insn_cou= nt) > + { > + insn1 > + =3D self->ops->read_memory_unsigned_integer (loc, 2,byte_order_for_code= ); > + loc +=3D 2; > + > + if (thumb_insn_size (insn1) !=3D 4) > + { > + /* Assume that there is at most one conditional branch in the > + atomic sequence. If a conditional branch is found, put a > + breakpoint in its destination address. */ > + if ((insn1 & 0xf000) =3D=3D 0xd000 && bits (insn1, 8, 11) !=3D 0x0f) > + { > + if (last_breakpoint > 0) > + return NULL; /* More than one conditional branch found, > + fallback to the standard code. */ > + > + breaks[1] =3D loc + 2 + (sbits (insn1, 0, 7) << 1); > + last_breakpoint++; > + } > + > + /* We do not support atomic sequences that use any *other* > + instructions but conditional branches to change the PC. > + Fall back to standard code to avoid losing control of > + execution. */ > + else if (thumb_instruction_changes_pc (insn1)) > + return NULL; > + } > + else > + { > + insn2 =3D self->ops->read_memory_unsigned_integer > + (loc, 2, byte_order_for_code); Format looks wrong, multiple instances of this problem in the patch. --=20 Yao (=E9=BD=90=E5=B0=A7)