From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 120048 invoked by alias); 13 Oct 2015 15:26:44 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 120031 invoked by uid 89); 13 Oct 2015 15:26:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-pa0-f54.google.com Received: from mail-pa0-f54.google.com (HELO mail-pa0-f54.google.com) (209.85.220.54) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 13 Oct 2015 15:26:40 +0000 Received: by pabrc13 with SMTP id rc13so24509769pab.0 for ; Tue, 13 Oct 2015 08:26:39 -0700 (PDT) X-Received: by 10.68.98.227 with SMTP id el3mr40563323pbb.20.1444749998916; Tue, 13 Oct 2015 08:26:38 -0700 (PDT) Received: from E107787-LIN (gcc2-power8.osuosl.org. [140.211.9.43]) by smtp.gmail.com with ESMTPSA id lo9sm4541701pab.19.2015.10.13.08.26.36 (version=TLS1_2 cipher=AES128-SHA256 bits=128/128); Tue, 13 Oct 2015 08:26:38 -0700 (PDT) From: Yao Qi To: Pedro Alves Cc: Yao Qi , gdb-patches@sourceware.org Subject: Re: [PATCH] aarch64 multi-arch part 6: HW breakpoint on unaligned address References: <1444731060-16237-1-git-send-email-yao.qi@linaro.org> <561CE5D2.8030505@redhat.com> Date: Tue, 13 Oct 2015 15:26:00 -0000 In-Reply-To: <561CE5D2.8030505@redhat.com> (Pedro Alves's message of "Tue, 13 Oct 2015 12:06:58 +0100") Message-ID: <861tcy6b84.fsf@gmail.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2015-10/txt/msg00173.txt.bz2 Pedro Alves writes: >> + { >> + if (len =3D=3D 3) >> + len =3D 2; > > I think this warrants a comment. E.g., someone reading > arm-linux-low.c:arm_linux_hw_point_initialize quite easily grasps > what 3 means. > How about the comment like this? if (len =3D=3D 3) { /* LEN is 3 means the breakpoint is set on a 32-bit thumb instruction. Set it to 2 to correctly encode length bit mask in hardware/watchpoint control register. */ len =3D 2; } >> diff --git a/gdb/nat/aarch64-linux-hw-point.c b/gdb/nat/aarch64-linux-hw= -point.c >> index bca6ec1..d15e518 100644 >> --- a/gdb/nat/aarch64-linux-hw-point.c >> +++ b/gdb/nat/aarch64-linux-hw-point.c >> @@ -112,8 +112,17 @@ aarch64_point_encode_ctrl_reg (enum target_hw_bp_ty= pe type, int len) >> static int >> aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len) >> { >> - unsigned int alignment =3D is_watchpoint ? AARCH64_HWP_ALIGNMENT >> - : AARCH64_HBP_ALIGNMENT; >> + unsigned int alignment =3D 0; >> + >> + if (is_watchpoint) >> + alignment =3D AARCH64_HWP_ALIGNMENT; >> + else >> + { >> + /* Set alignment to 2 only if the current process is 32-bit, >> + since thumb instruction can be 2-byte aligned. Otherwise, set >> + alignment to AARCH64_HBP_ALIGNMENT. */ >> + alignment =3D 2; > > Is some other code doing what the comment says? I'm not seeing > any obvious 32-bit check. No, I don't do the 32-bit check here. Ideally, we should set alignment to 2 only when the process is 32-bit, and still use 4 as alignment otherwise. However, I don't find an easy way to do the 32-bit check here, because this code is used by both GDB and GDBserver. We can do the 32-bit check in GDB and GDBserver respectively, and pass the result to nat/aarch64-linux-hw-point.c, but I don't like putting information down multiple levels like this. --=20 Yao (=E9=BD=90=E5=B0=A7)