From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 56975 invoked by alias); 17 Mar 2017 09:36:06 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 56200 invoked by uid 89); 17 Mar 2017 09:36:05 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:1345 X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 17 Mar 2017 09:36:03 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cooIk-0007Ue-6a for gdb-patches@sourceware.org; Fri, 17 Mar 2017 05:36:03 -0400 Received: from fencepost.gnu.org ([2001:4830:134:3::e]:60107) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cooIa-0007Pi-SV; Fri, 17 Mar 2017 05:35:53 -0400 Received: from 84.94.185.246.cable.012.net.il ([84.94.185.246]:3506 helo=home-c4e4a596f7) by fencepost.gnu.org with esmtpsa (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.82) (envelope-from ) id 1cooIa-0001te-1m; Fri, 17 Mar 2017 05:35:52 -0400 Date: Fri, 17 Mar 2017 09:36:00 -0000 Message-Id: <83fuicz1nk.fsf@gnu.org> From: Eli Zaretskii To: Stafford Horne CC: gdb-patches@sourceware.org, franck.jullien@gmail.com, openrisc@lists.librecores.org In-reply-to: <20170317093247.GO2418@lianli.shorne-pla.net> (message from Stafford Horne on Fri, 17 Mar 2017 18:32:47 +0900) Subject: Re: [PATCH v5 1/4] gdb: Add OpenRISC or1k and or1knd target support Reply-to: Eli Zaretskii References: <61be7be503333904f9533549b0a809bed4066ac3.1489728533.git.shorne@gmail.com> <83lgs4z3ty.fsf@gnu.org> <20170317093247.GO2418@lianli.shorne-pla.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:4830:134:3::e X-IsSubscribed: yes X-SW-Source: 2017-03/txt/msg00309.txt.bz2 > Date: Fri, 17 Mar 2017 18:32:47 +0900 > From: Stafford Horne > Cc: gdb-patches@sourceware.org, franck.jullien@gmail.com, > openrisc@lists.librecores.org > > > > +The OpenRISC 1000 architecture has evolved since the first port for > > > +@value{GDBN}. In particular the structure of the Unit Present register has > > > +changed and the CPU Configuration register has been added. The port of > > > +@value{GDBN} version @value{GDBVN} uses the @emph{current} > > > +specification of the OpenRISC 1000. > > > > I'm not sure what this text conveys. Can you tell why it is important > > to have this information in the manual? I might then suggest a change > > in wording. > > Its saying that if you are using an old version of the CPU it might not > run as expected with this version of GDB. Ill change to explain that > without talking about previous ports of GDB. > > Something like: > > Earlier version of the OpenRISC architecture did not include the UPR > (unit present) or CPUCFGR (CPU configuration) registers. This version > of @value{GDBN} expects these to be present. That's okay, but we should also tell the reader what to do if the expected registers are not present. Is there anything they could do except upgrade to a newer version of OpenRISC?