From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 78106 invoked by alias); 14 Aug 2015 20:32:16 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 78093 invoked by uid 89); 14 Aug 2015 20:32:15 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_SOFTFAIL autolearn=no version=3.3.2 X-HELO: mtaout27.012.net.il Received: from mtaout27.012.net.il (HELO mtaout27.012.net.il) (80.179.55.183) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 14 Aug 2015 20:32:12 +0000 Received: from conversion-daemon.mtaout27.012.net.il by mtaout27.012.net.il (HyperSendmail v2007.08) id <0NT300K009XSRY00@mtaout27.012.net.il> for gdb-patches@sourceware.org; Fri, 14 Aug 2015 23:29:20 +0300 (IDT) Received: from HOME-C4E4A596F7 ([87.69.4.28]) by mtaout27.012.net.il (HyperSendmail v2007.08) with ESMTPA id <0NT300JIPA8WJB20@mtaout27.012.net.il>; Fri, 14 Aug 2015 23:29:20 +0300 (IDT) Date: Fri, 14 Aug 2015 20:32:00 -0000 From: Eli Zaretskii Subject: Re: [rfc] btrace: change record instruction-history /m In-reply-to: To: Doug Evans Cc: markus.t.metzger@intel.com, palves@redhat.com, gdb-patches@sourceware.org Reply-to: Eli Zaretskii Message-id: <834mk1obll.fsf@gnu.org> References: <1439552272-6256-1-git-send-email-markus.t.metzger@intel.com> <83bneanfvb.fsf@gnu.org> X-IsSubscribed: yes X-SW-Source: 2015-08/txt/msg00393.txt.bz2 > From: Doug Evans > Date: Fri, 14 Aug 2015 10:06:15 -0700 > Cc: Markus Metzger , Pedro Alves , > gdb-patches > > On Fri, Aug 14, 2015 at 6:45 AM, Eli Zaretskii wrote: > >> From: Markus Metzger > >> Cc: gdb-patches@sourceware.org, dje@google.com > >> Date: Fri, 14 Aug 2015 13:37:52 +0200 > >> > >> Change record instruction-history /m to use its own simple source interleaving > >> algorithm. The most important part is that instructions are printed in > >> the order in which they were executed. > > > > What does "order in which they were executed" mean with today's > > multi-core and multi-execution unit CPUs? > > > > Thanks. > > "multi-core" doesn't enter into the picture here. > The context is a single thread of control. > And "multi-execution unit" doesn't either because > that's just an underlying implementation detail > of the CPU - the program must behave "as if" > each instruction is executed serially > (or as otherwise defined by the ISA). You and I know that, but the text makes it sound as if each instruction was somehow stamped with its execution time, and then the instruction stream presented in that order, after annotating each instruction with its source. And that's misleading, IMO, because evidently that's not what will happen.