From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id EqzBEs9u8mL/uiMAWB0awg (envelope-from ) for ; Tue, 09 Aug 2022 10:27:27 -0400 Received: by simark.ca (Postfix, from userid 112) id 3D0631E5EA; Tue, 9 Aug 2022 10:27:27 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-3.9 required=5.0 tests=BAYES_00,MAILING_LIST_MULTI, NICE_REPLY_A,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 1A8151E13B for ; Tue, 9 Aug 2022 10:27:26 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 45A923856DC2 for ; Tue, 9 Aug 2022 14:27:25 +0000 (GMT) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 7D3353856DC2 for ; Tue, 9 Aug 2022 14:27:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7D3353856DC2 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from [192.168.68.105] (unknown [111.18.133.247]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Dx4M65bvJiHy0LAA--.33299S3; Tue, 09 Aug 2022 22:27:06 +0800 (CST) Message-ID: <7631ce1e-b31b-6e45-151c-bc6aaf438b0e@loongson.cn> Date: Tue, 9 Aug 2022 22:27:06 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.4.0 Subject: Re: [PATCH v2] gdb/gdbserver: LoongArch: Improve implementation of fcc registers Content-Language: en-US To: Feiyang Chen References: <20220802091656.55802-1-chenfeiyang@loongson.cn> From: Tiezhu Yang In-Reply-To: <20220802091656.55802-1-chenfeiyang@loongson.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CM-TRANSID: AQAAf9Dx4M65bvJiHy0LAA--.33299S3 X-Coremail-Antispam: 1UD129KBjvJXoW7uF4xJry8tF1xWr1rKFWkCrg_yoW8Xr4kpa yrua43JF4kGrW7ZFZIg3W5WF15GFZ7GrWxZFnIy34jvF4DGF9Yqw18JrZIgF1UGr1xCrWI qa4Fkw4j9FWUCrJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkSb7Iv0xC_Kw4lb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rw A2F7IY1VAKz4vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xII jxv20xvEc7CjxVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4 A2jsIEc7CjxVAFwI0_GcCE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IE w4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMc vjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvEwIxGrwCYjI0SjxkI62AI1cAE67vIY487MxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUXVWUAwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_WFyUJVCq3wCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY 6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxUgg_TUUUUU X-CM-SenderInfo: p1dqw3xlh2x3gn0dqz5rrqw2lrqou0/ X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Feiyang Chen , gdb-patches@sourceware.org Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" On 8/2/22 17:16, Feiyang Chen wrote: > The current implementation of the fcc register is referenced to the > user_fp_state structure of the kernel uapi [1]. But it is mistakenly > defined as a 64-bit fputype register, resulting in in a confusing > output of "info register". > > (gdb) info register > ... > fcc {f = 0x0, d = 0x0} {f = 0, d = 0} > ... > > According to "Condition Flag Register" in "LoongArch Reference Manual" > [2], there are 8 condition flag registers of size 1. Use 8 registers of > uint8 to make it easier for users to view the fcc register groups. > > (gdb) info register > ... > fcc0 0x1 1 > fcc1 0x0 0 > fcc2 0x0 0 > fcc3 0x0 0 > fcc4 0x0 0 > fcc5 0x0 0 > fcc6 0x0 0 > fcc7 0x0 0 > ... > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/uapi/asm/ptrace.h > [2] https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_condition_flag_register > > Signed-off-by: Feiyang Chen > --- > gdb/arch/loongarch.h | 7 ++-- > gdb/features/loongarch/fpu.c | 9 +++++- > gdb/features/loongarch/fpu.xml | 9 +++++- > gdb/loongarch-linux-tdep.c | 55 +++++++++++++++++++++++++++++--- > gdb/loongarch-tdep.c | 6 ++-- > gdbserver/linux-loongarch-low.cc | 24 ++++++++++++++ > 6 files changed, 99 insertions(+), 11 deletions(-) Thanks for the detailed commit message in this version. Looks good to me, tested on LoongArch, pushed. Thanks, Tiezhu