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Thu, 10 Sep 2026 16:54:08 +0000 Date: Thu, 10 Sep 2026 16:54:04 +0000 (UTC) From: Hannes Domani To: "Rohr, Stephan" , "gdb-patches@sourceware.org" , "Joos, Christina" Cc: Tom Tromey Message-ID: <7376680.1510.1789059244617@mail.yahoo.com> In-Reply-To: References: <20260829145823.1034821-1-ssbssa@yahoo.de> <20260829145823.1034821-8-ssbssa@yahoo.de> Subject: Re: [PATCH v3 8/8] Windows gdb: Implement AVX-512 register support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Mailer: WebService/1.1.26525 YMailCLDNorrin X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org I'm not sure what happened, but I replied earlier to 8/8 already, but with the contents to my reply for 7/8... Am Donnerstag, 10. September 2026 um 14:08:10 MESZ hat Joos, Christina Folgendes geschrieben: > Hi Hannes, >=C2=A0 > Thank you for this patch and your work on this. >=C2=A0 > Please find my comments on top of Stephan's feedback. >=C2=A0 > > -----Original Message----- > > From: Rohr, Stephan > > Sent: Dienstag, 8. September 2026 15:05 > > To: Hannes Domani ; gdb-patches@sourceware.org > > Cc: Joos, Christina ; Tom Tromey > > > > Subject: RE: [PATCH v3 8/8] Windows gdb: Implement AVX-512 register sup= port > > > > Hi Hannes, > > > > please see some inline feedback below. > > Some of the feedback provided for > > > >=C2=A0 [PATCH v3 7/8] Windows gdb: Implement AVX register support > > > > applies here as well. > > > > Thanks > > > > Stephan > > > > > -----Original Message----- > > > From: Hannes Domani > > > Sent: Saturday, 29 August 2026 16:49 > > > To: gdb-patches@sourceware.org > > > Subject: [PATCH v3 8/8] Windows gdb: Implement AVX-512 register > > > support > > > > > > This adds support for the Intel AVX-512 registers on Windows. > > > It enables accessing registers $ymm0 - $ymm31, $zmm0 - $zmm31, and > > > $k0 - $k7 where they are available. >=C2=A0 > Suggestion: > For the linux side we have this commit to enable AMX-512: > " Add AVX512 registers support to GDB and GDBserver." >=C2=A0 > It includes a description which registers are added, extended etc: >=C2=A0 > " Intel(R) AVX-512 is an extension to AVX to support 512-bit wide > SIMD registers in 64-bit mode (XMM0-XMM31, YMM0-YMM31, ZMM0-ZMM31). > The number of available registers in 32-bit mode is still 8 > (XMM0-7, YMM0-7, ZMM0-7).=C2=A0 The lower 256-bits of the ZMM registers > are aliased to the respective 256-bit YMM registers.=C2=A0 The lower > 128-bits are aliased to the respective 128-bit XMM registers. >=C2=A0 > There are also 8 new, dedicated mask registers (K0-K7) in both 32-bit > mode and 64-bit mode." >=C2=A0 > Maybe you could reference it, something like > "similar to commit xyz for linux this patch adds [...] for 32 and 64-bit = mode in windows." ? >=C2=A0 > Then you have all the details described, if one would like to look it up = to understand your > patch in detail. But you don't have to repeat it in your own commit messa= ge. >=C2=A0 > What do you think? Sounds good. > > > After this patch gdb.arch/i386-avx512.exp passes on windows. > > > --- > > > v3: > > >=C2=A0 - merged gdb+gdbserver parts, and split again AVX/AVX-512 parts > > > --- > > >=C2=A0 gdb/NEWS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 |=C2=A0 2 ++ > > >=C2=A0 gdb/nat/windows-nat.c=C2=A0 =C2=A0 =C2=A0 |=C2=A0 2 +- > > >=C2=A0 gdb/x86-windows-nat.c=C2=A0 =C2=A0 =C2=A0 | 35 ++++++++++++++++= +++++++++++ > > >=C2=A0 gdbserver/win32-i386-low.cc | 48 > > > ++++++++++++++++++++++++++++++++++++- > > >=C2=A0 4 files changed, 85 insertions(+), 2 deletions(-) > > > > > > diff --git a/gdb/NEWS b/gdb/NEWS > > > index f7effc822e9..d3db6dd167e 100644 > > > --- a/gdb/NEWS > > > +++ b/gdb/NEWS > > > @@ -120,6 +120,8 @@ > > > > > >=C2=A0 * Support for Intel AVX registers on Windows. > > >=C2=A0 =C2=A0 Support displaying and modifying Intel AVX registers $ym= m0 - $ymm31. > > > > Following the previous patch, this should update again to registers $ym= m0 - > > $ymm31? Right. > > > +=C2=A0 Support displaying and modifying Intel AVX-512 registers $zmm= 0 - > > > + $zmm31=C2=A0 and $k0 - $k7. > > > > > >=C2=A0 * Configure changes > > > > > > diff --git a/gdb/nat/windows-nat.c b/gdb/nat/windows-nat.c index > > > c9a21d7c41f..30d49c07332 100644 > > > --- a/gdb/nat/windows-nat.c > > > +++ b/gdb/nat/windows-nat.c > > > @@ -1339,7 +1339,7 @@ initialize_loadable () > > >=C2=A0 =C2=A0 =C2=A0 { > > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Available XState features masked with i= mplemented features.=C2=A0 */ > > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 xstate_features =3D (GetEnabledXStateFeatu= res () > > > -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 & X86_XSTATE_AVX_MASK); > > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 & X86_XSTATE_AVX_AVX512_MA= SK); > > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* The extended XState functions are only = needed if the available > > >=C2=A0 =C2=A0 =C2=A0 features exceed SSE.=C2=A0 */ > > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 if ((xstate_features & ~X86_XSTATE_SSE_MAS= K) =3D=3D 0) diff --git > > > a/gdb/x86-windows-nat.c b/gdb/x86-windows-nat.c index > > > 1cefe6171be..425e343deca 100644 > > > --- a/gdb/x86-windows-nat.c > > > +++ b/gdb/x86-windows-nat.c > > > @@ -291,6 +291,41 @@ get_context_reg_ptr (Context *context, int r, > > > i386_gdbarch_tdep *tdep) > > >=C2=A0 =C2=A0 =C2=A0 (context, X86_XSTATE_AVX_ID, NULL); > > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 context_offset +=3D 16 * (r - I387_YMM0H_R= EGNUM (tdep)); > > >=C2=A0 =C2=A0 =C2=A0 } > > > +=C2=A0 else if (I387_ZMM0H_REGNUM (tdep) > 0 && r >=3D > > I387_ZMM0H_REGNUM > > > (tdep) > > > +=C2=A0 =C2=A0 =C2=A0 && r < I387_ZMM16H_REGNUM (tdep) && r < > > > I387_ZMMENDH_REGNUM (tdep)) > > > +=C2=A0 =C2=A0 { > > > > I basically have the same concern as in patch 7/8 regarding the guards = on > > gdbserver side but missing here. > > > > > +=C2=A0 =C2=A0 =C2=A0 context_offset =3D (char *) locate_xstate_featu= re > > > +=C2=A0 =C2=A0 (context, X86_XSTATE_ZMM_H_ID, NULL); > > > +=C2=A0 =C2=A0 =C2=A0 context_offset +=3D 32 * (r - I387_ZMM0H_REGNUM= (tdep)); > > > +=C2=A0 =C2=A0 } > > > +=C2=A0 else if (I387_ZMM0H_REGNUM (tdep) > 0 && r >=3D > > > I387_ZMM16H_REGNUM (tdep) > > > +=C2=A0 =C2=A0 =C2=A0 && r < I387_ZMMENDH_REGNUM (tdep)) > > > +=C2=A0 =C2=A0 { > > > +=C2=A0 =C2=A0 =C2=A0 context_offset =3D (char *) locate_xstate_featu= re > > > +=C2=A0 =C2=A0 (context, X86_XSTATE_ZMM_ID, NULL); > > > +=C2=A0 =C2=A0 =C2=A0 context_offset +=3D 32 + 64 * (r - I387_ZMM16H_= REGNUM (tdep)); > > > +=C2=A0 =C2=A0 } > > > +=C2=A0 else if (I387_K0_REGNUM (tdep) > 0 && r >=3D I387_K0_REGNUM (= tdep) > > > +=C2=A0 =C2=A0 =C2=A0 && r < I387_KEND_REGNUM (tdep)) > > > +=C2=A0 =C2=A0 { > > > +=C2=A0 =C2=A0 =C2=A0 context_offset =3D (char *) locate_xstate_featu= re > > > +=C2=A0 =C2=A0 (context, X86_XSTATE_K_ID, NULL); > > > +=C2=A0 =C2=A0 =C2=A0 context_offset +=3D 8 * (r - I387_K0_REGNUM (td= ep)); > > > +=C2=A0 =C2=A0 } > > > +=C2=A0 else if (I387_YMM16H_REGNUM (tdep) > 0 && r >=3D > > > I387_YMM16H_REGNUM (tdep) > > > +=C2=A0 =C2=A0 =C2=A0 && r < I387_YMMH_AVX512_END_REGNUM (tdep)) > > > +=C2=A0 =C2=A0 { > > > +=C2=A0 =C2=A0 =C2=A0 context_offset =3D (char *) locate_xstate_featu= re > > > +=C2=A0 =C2=A0 (context, X86_XSTATE_ZMM_ID, NULL); > > > +=C2=A0 =C2=A0 =C2=A0 context_offset +=3D 16 + 64 * (r - I387_YMM16H_= REGNUM (tdep)); > > > +=C2=A0 =C2=A0 } > > > +=C2=A0 else if (I387_XMM16_REGNUM (tdep) > 0 && r >=3D I387_XMM16_RE= GNUM > > > (tdep) > > > +=C2=A0 =C2=A0 =C2=A0 && r < I387_XMM_AVX512_END_REGNUM (tdep)) > > > +=C2=A0 =C2=A0 { > > > +=C2=A0 =C2=A0 =C2=A0 context_offset =3D (char *) locate_xstate_featu= re > > > +=C2=A0 =C2=A0 (context, X86_XSTATE_ZMM_ID, NULL); > > > +=C2=A0 =C2=A0 =C2=A0 context_offset +=3D 64 * (r - I387_XMM16_REGNUM= (tdep)); > > > +=C2=A0 =C2=A0 } > > >=C2=A0 =C2=A0 else > > >=C2=A0 =C2=A0 =C2=A0 gdb_assert_not_reached ("invalid register number = %d", r); > > > > > > diff --git a/gdbserver/win32-i386-low.cc b/gdbserver/win32-i386-low.c= c > > > index a7e83c0239c..6911587f977 100644 > > > --- a/gdbserver/win32-i386-low.cc > > > +++ b/gdbserver/win32-i386-low.cc > > > @@ -529,8 +529,11 @@ get_context_reg_ptr (Context *context, int r, > > > const target_desc *tdesc) > > >=C2=A0 =C2=A0 =C2=A0 } > > > > > >=C2=A0 =C2=A0 bool amd64 =3D register_size (tdesc, 0) =3D=3D 8; > > > -=C2=A0 int ymm0h_regnum; > > > +=C2=A0 int ymm0h_regnum, zmm0h_regnum, k0_regnum;=C2=A0 int xmm16_re= gnum, > > > + ymm16h_regnum, zmm16h_regnum; > > >=C2=A0 =C2=A0 const int num_xmm_registers =3D amd64 ? 16 : 8; > > > +=C2=A0 const int num_zmm_high_registers =3D amd64 ? 16 : 0;=C2=A0 co= nst int > > > + num_avx512_k_registers =3D 8; > > > > > >=C2=A0 =C2=A0 char *context_offset; > > >=C2=A0 =C2=A0 if (r < mappings_count) > > > @@ -543,6 +546,49 @@ get_context_reg_ptr (Context *context, int r, > > > const target_desc *tdesc) > > >=C2=A0 =C2=A0 =C2=A0 (context, X86_XSTATE_AVX_ID, NULL); > > >=C2=A0 =C2=A0 =C2=A0 =C2=A0 context_offset +=3D 16 * (r - ymm0h_regnum= ); > > >=C2=A0 =C2=A0 =C2=A0 } > > > +=C2=A0 else if ((xstate_features & X86_XSTATE_ZMM_H) !=3D 0 > > > +=C2=A0 =C2=A0 =C2=A0 && r >=3D (zmm0h_regnum =3D find_regno (tdesc, = "zmm0h")) > > > +=C2=A0 =C2=A0 =C2=A0 && r < zmm0h_regnum + num_xmm_registers) > > > +=C2=A0 =C2=A0 { > > > +=C2=A0 =C2=A0 =C2=A0 context_offset =3D (char *) locate_xstate_featu= re > > > +=C2=A0 =C2=A0 (context, X86_XSTATE_ZMM_H_ID, NULL); > > > +=C2=A0 =C2=A0 =C2=A0 context_offset +=3D 32 * (r - zmm0h_regnum); > > > +=C2=A0 =C2=A0 } >=C2=A0 > Similar comment=C2=A0 to the previous patch for nullptr here and below. >=C2=A0 > > > +=C2=A0 else if ((xstate_features & X86_XSTATE_ZMM) !=3D 0 > > > +=C2=A0 =C2=A0 =C2=A0 && num_zmm_high_registers !=3D 0 > > > +=C2=A0 =C2=A0 =C2=A0 && r >=3D (zmm16h_regnum =3D find_regno (tdesc,= "zmm16h")) > > > +=C2=A0 =C2=A0 =C2=A0 && r < zmm16h_regnum + num_zmm_high_registers) > > > +=C2=A0 =C2=A0 { > > > +=C2=A0 =C2=A0 =C2=A0 context_offset =3D (char *) locate_xstate_featu= re > > > +=C2=A0 =C2=A0 (context, X86_XSTATE_ZMM_ID, NULL); > > > +=C2=A0 =C2=A0 =C2=A0 context_offset +=3D 32 + 64 * (r - zmm16h_regnu= m); > > > +=C2=A0 =C2=A0 } > > > +=C2=A0 else if ((xstate_features & X86_XSTATE_K) !=3D 0 > > > +=C2=A0 =C2=A0 =C2=A0 && r >=3D (k0_regnum =3D find_regno (tdesc, "k0= ")) > > > +=C2=A0 =C2=A0 =C2=A0 && r < k0_regnum + num_avx512_k_registers) > > > +=C2=A0 =C2=A0 { > > > +=C2=A0 =C2=A0 =C2=A0 context_offset =3D (char *) locate_xstate_featu= re > > > +=C2=A0 =C2=A0 (context, X86_XSTATE_K_ID, NULL); > > > +=C2=A0 =C2=A0 =C2=A0 context_offset +=3D 8 * (r - k0_regnum); > > > +=C2=A0 =C2=A0 } > > > +=C2=A0 else if ((xstate_features & X86_XSTATE_ZMM) !=3D 0 > > > +=C2=A0 =C2=A0 =C2=A0 && num_zmm_high_registers !=3D 0 > > > +=C2=A0 =C2=A0 =C2=A0 && r >=3D (ymm16h_regnum =3D find_regno (tdesc,= "ymm16h")) > > > +=C2=A0 =C2=A0 =C2=A0 && r < ymm16h_regnum + num_zmm_high_registers) > > > +=C2=A0 =C2=A0 { > > > +=C2=A0 =C2=A0 =C2=A0 context_offset =3D (char *) locate_xstate_featu= re > > > +=C2=A0 =C2=A0 (context, X86_XSTATE_ZMM_ID, NULL); > > > +=C2=A0 =C2=A0 =C2=A0 context_offset +=3D 16 + 64 * (r - ymm16h_regnu= m); > > > +=C2=A0 =C2=A0 } > > > +=C2=A0 else if ((xstate_features & X86_XSTATE_ZMM) !=3D 0 > > > +=C2=A0 =C2=A0 =C2=A0 && num_zmm_high_registers !=3D 0 > > > +=C2=A0 =C2=A0 =C2=A0 && r >=3D (xmm16_regnum =3D find_regno (tdesc, = "xmm16")) > > > +=C2=A0 =C2=A0 =C2=A0 && r < xmm16_regnum + num_zmm_high_registers) > > > +=C2=A0 =C2=A0 { > > > +=C2=A0 =C2=A0 =C2=A0 context_offset =3D (char *) locate_xstate_featu= re > > > +=C2=A0 =C2=A0 (context, X86_XSTATE_ZMM_ID, NULL); > > > +=C2=A0 =C2=A0 =C2=A0 context_offset +=3D 64 * (r - xmm16_regnum); > > > +=C2=A0 =C2=A0 } > > >=C2=A0 =C2=A0 else > > >=C2=A0 =C2=A0 =C2=A0 gdb_assert_not_reached ("invalid register number = %d", r); > > > > > > > These are a lot of look-ups on gdbserver side.=C2=A0 Each "find_regno" = iterates over > > the complete set of registers and does string comparison.=C2=A0 It woul= d be nice to > > implement this like the GDB side and cache the register numbers. > > > > I think it is not mandatory to implement this but would be nice to have= . >=C2=A0 > I have a similar comment on this, but for the offsets: >=C2=A0 > Those offsets are similar in gdbserver/i387-fp.cc and gdb/i387-tdep.c, bu= t we > cannot use/share the complete logic for windows gdb & gdbserver I believe= . >=C2=A0 > However, the offsets inside one feature (I don't mean the offsets between= two > consecutive features) should be the same for any OS and independent of AM= D or Intel. > I believe it would be nice if we could at least share the offset calculat= ions at some point > maybe in gdbsupport/* sometime in future... > But this is nothing that you must do as part of this patch of course. >=C2=A0 > For this patch: > I don't think this is strictly necessary, but we could make this code a b= it more generic inside each individual file on gdb & gdbserver side. > For example, we could introduce some static helpers or similar, that are = called in each else if. > What do you think? >=C2=A0 > Christina I was also thinking that these look-ups are not ideal. As I understand it, the offsets for each feature are not fixed values on windows, but they should be the same for all threads on a system. In that case, maybe we could calculate these offsets for all registers once, put them in a vector, and use that in get_context_reg_ptr? I'm also assuming that the register numbers always stay the same. I'm just not sure at which point the offset calculation should be done. Any suggestions? Hannes