From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id wA99FzHm/WNbeAAAWB0awg (envelope-from ) for ; Tue, 28 Feb 2023 06:32:01 -0500 Received: by simark.ca (Postfix, from userid 112) id 5B74B1E222; Tue, 28 Feb 2023 06:32:01 -0500 (EST) Authentication-Results: simark.ca; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.a=rsa-sha256 header.s=default header.b=rShJkNtb; dkim-atps=neutral X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI, RDNS_DYNAMIC,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id D907B1E128 for ; Tue, 28 Feb 2023 06:32:00 -0500 (EST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 47086384D146 for ; Tue, 28 Feb 2023 11:32:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 47086384D146 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1677583920; bh=S9UNjCgf0c4tSDKL0aw3yaRmSC3V0+UKpjI3y3/N8Is=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=rShJkNtbzbCK45UIihc8GsDx2lgIXQS3T1Ax1saUMAy6uJXCxqX/hdfAKVJp6vPbL QhdePx5RFV+/kfIPQCkVB/rySjZe7FYOalR2b/UH3i7njaIjTvCOzPMvZ/gkPkqYXL M5GuTSNK8F12dyLerzFz6oAUQElizMpsa6kg0Pes= Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id CEF1138515DB for ; Tue, 28 Feb 2023 11:30:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CEF1138515DB X-IronPort-AV: E=McAfee;i="6500,9779,10634"; a="313785106" X-IronPort-AV: E=Sophos;i="5.98,221,1673942400"; d="scan'208";a="313785106" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2023 03:30:32 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10634"; a="623992172" X-IronPort-AV: E=Sophos;i="5.98,221,1673942400"; d="scan'208";a="623992172" Received: from ultl2604.iul.intel.com (HELO localhost) ([172.28.48.47]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2023 03:30:31 -0800 To: gdb-patches@sourceware.org Subject: [PATCH 17/26] gdbserver: rename regcache's registers_valid to registers_fetched Date: Tue, 28 Feb 2023 12:28:15 +0100 Message-Id: <7296899ef77a86051c398fc1c20338f2937386eb.1677582745.git.tankut.baris.aktemur@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Tankut Baris Aktemur via Gdb-patches Reply-To: Tankut Baris Aktemur Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" The registers_valid field of the regcache struct is used for tracking whether we have attempted to fetch all the registers from the target. Its name does not reflect this well, I think. It falsely gives the impression that all the registers are valid. This may conflict an individual register status, which could be REG_UNAVAILABLE. To better reflect the purpose, rename the field to "registers_fetched". --- gdbserver/regcache.cc | 12 ++++++------ gdbserver/regcache.h | 13 +++++++------ 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/gdbserver/regcache.cc b/gdbserver/regcache.cc index 4b56750d06a..0e21c1aa7d1 100644 --- a/gdbserver/regcache.cc +++ b/gdbserver/regcache.cc @@ -57,7 +57,7 @@ get_thread_regcache (struct thread_info *thread, bool fetch) void regcache::fetch () { - if (!registers_valid) + if (!registers_fetched) { scoped_restore_current_thread restore_thread; gdb_assert (this->thread != nullptr); @@ -66,7 +66,7 @@ regcache::fetch () /* Invalidate all registers, to prevent stale left-overs. */ memset (register_status, REG_UNAVAILABLE, tdesc->reg_defs.size ()); fetch_inferior_registers (this, -1); - registers_valid = true; + registers_fetched = true; } } @@ -92,7 +92,7 @@ regcache_invalidate_thread (struct thread_info *thread) void regcache::invalidate () { - if (registers_valid) + if (registers_fetched) { scoped_restore_current_thread restore_thread; gdb_assert (this->thread != nullptr); @@ -128,7 +128,7 @@ regcache_invalidate (void) void regcache::discard () { - registers_valid = false; + registers_fetched = false; } void @@ -164,7 +164,7 @@ regcache::initialize (const target_desc *tdesc, #endif } - this->registers_valid = false; + this->registers_fetched = false; } #ifndef IN_PROCESS_AGENT @@ -197,7 +197,7 @@ regcache::copy_from (regcache *src) memcpy (this->register_status, src->register_status, src->tdesc->reg_defs.size ()); #endif - this->registers_valid = src->registers_valid; + this->registers_fetched = src->registers_fetched; } /* Return a reference to the description of register N. */ diff --git a/gdbserver/regcache.h b/gdbserver/regcache.h index f155ac631eb..3fcd4643a42 100644 --- a/gdbserver/regcache.h +++ b/gdbserver/regcache.h @@ -36,12 +36,13 @@ struct regcache : public reg_buffer_common /* Back-link to the thread to which this regcache belongs. */ thread_info *thread = nullptr; - /* Whether the REGISTERS buffer's contents are valid. If false, we - haven't fetched the registers from the target yet. Not that this - register cache is _not_ pass-through, unlike GDB's. Note that - "valid" here is unrelated to whether the registers are available - in a traceframe. For that, check REGISTER_STATUS below. */ - bool registers_valid = false; + /* Whether the REGISTERS buffer's contents are fetched. If false, + we haven't fetched the registers from the target yet. Note that + this register cache is _not_ pass-through, unlike GDB's. Also, + note that "fetched" here is unrelated to whether the registers + are available in a traceframe. For that, check REGISTER_STATUS + below. */ + bool registers_fetched = false; bool registers_owned = false; unsigned char *registers = nullptr; #ifndef IN_PROCESS_AGENT -- 2.25.1 Intel Deutschland GmbH Registered Address: Am Campeon 10, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Christin Eisenschmid, Sharon Heck, Tiffany Doon Silva Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928