[SH] Check FPSCR.PR for fldi0, fldi1 insns in simulator

Oleg Endo
2026-03-11T03:02:55Z

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Hi,

On SH variants with double-precision FPU the insns fli0 and flid1 require
that FPSCR.PR must be set to 0, i.e. single-precision mode. The attached
patch fixes that.

OK to apply?

Best regards,
Oleg Endo

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From 3417353c867efd502da6df1e80b9a8bdb0a422f0 Mon Sep 17 00:00:00 2001
From: Oleg Endo <olegendo@gcc.gnu.org>
Date: Wed, 11 Mar 2026 11:55:20 +0900
Subject: [PATCH] sim/sh: check PFSCR.PR setting for fldi0 and fldi1 insns

---
sim/sh/gencode.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/sim/sh/gencode.c b/sim/sh/gencode.c
index 42009fc..9c882d2 100644
--- a/sim/sh/gencode.c
+++ b/sim/sh/gencode.c
@@ -644,18 +644,22 @@ static op tab[] =

/* sh2e */
{ "", "", "fldi0 <FREG_N>", "1111nnnn10001101",
{
- "SET_FR (n, (float) 0.0);",
- "/* FIXME: check for DP and (n & 1) == 0? */",
+ "if (FPSCR_PR)",
+ " RAISE_EXCEPTION (SIGILL);",
+ "else",
+ " SET_FR (n, (float) 0.0);",
},
},

/* sh2e */
{ "", "", "fldi1 <FREG_N>", "1111nnnn10011101",
{
- "SET_FR (n, (float) 1.0);",
- "/* FIXME: check for DP and (n & 1) == 0? */",
+ "if (FPSCR_PR)",
+ " RAISE_EXCEPTION (SIGILL);",
+ "else",
+ " SET_FR (n, (float) 1.0);",
},
},

/* sh2e */
--
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