From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id S2eTCkHvsGkoKyMAWB0awg (envelope-from ) for ; Wed, 11 Mar 2026 00:27:45 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=simark.ca; s=mail; t=1773203265; bh=e73Y1hkGjR/vsBPb+qHxhG9tH5KStXnA3Ylj9EZSR90=; h=Date:Subject:To:References:From:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=ZUNA+h1Nmf07GXkZ/lIx8bozo87Caey2XJH6Y0vgBubF3Q1r2PQbp0gaTOOZRdPOq 0N87zo7TUu8xrO9oEZi3eaxOC5PAF8R2AncCEHFQvUoAx84W6TCsKGUjbqqCnkfFN+ ppv/KSSfCzTLsFQYT1S4QTZQTmK22hXnq3Z8IhtM= Received: by simark.ca (Postfix, from userid 112) id 116141E0DD; Wed, 11 Mar 2026 00:27:45 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-25) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-2.4 required=5.0 tests=ARC_SIGNED,ARC_VALID,BAYES_00, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED, RCVD_IN_VALIDITY_RPBL_BLOCKED,RCVD_IN_VALIDITY_SAFE_BLOCKED autolearn=ham autolearn_force=no version=4.0.1 Authentication-Results: simark.ca; dkim=pass (1024-bit key; unprotected) header.d=simark.ca header.i=@simark.ca header.a=rsa-sha256 header.s=mail header.b=bzH946UX; dkim-atps=neutral Received: from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 19C091E08D for ; Wed, 11 Mar 2026 00:27:44 -0400 (EDT) Received: from vm01.sourceware.org (localhost [127.0.0.1]) by sourceware.org (Postfix) with ESMTP id 9E9FA4B9700A for ; Wed, 11 Mar 2026 04:27:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9E9FA4B9700A Authentication-Results: sourceware.org; dkim=pass (1024-bit key, unprotected) header.d=simark.ca header.i=@simark.ca header.a=rsa-sha256 header.s=mail header.b=bzH946UX Received: from simark.ca (simark.ca [158.69.221.121]) by sourceware.org (Postfix) with ESMTPS id 5125A4BAE7D6 for ; Wed, 11 Mar 2026 04:27:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5125A4BAE7D6 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=simark.ca Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=simark.ca ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 5125A4BAE7D6 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=158.69.221.121 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1773203236; cv=none; b=VJjdwkzaImsJKwlZQYx91kq3GwZsT5QfO3TxDOPsdBXosdpugwr/Ut7eboTtpKpInZPKw+N08ZqaeqRPMdNp0PJFvR25IBLK3NMvO4UWVvNOJ3YjcDt+FznpjAGvyU14UEs0F0I6oLH3xPqPvha2GsqAzEk7RTUzW+RAqK1adLo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1773203236; c=relaxed/simple; bh=e73Y1hkGjR/vsBPb+qHxhG9tH5KStXnA3Ylj9EZSR90=; h=DKIM-Signature:Message-ID:Date:MIME-Version:Subject:To:From; b=N0gHkZvSUGXSMwjLxpIal6hgDT7w+nEML/YN3RdUHoDJQRYffK1GxVxqc8pcu+5GMJs3FMgjUUoTpNbR2VAfo+hDpmRvzFvPsGiBTOazogXYasPWQGW9kvQSZ8oN1GME/r8lNPOouY0WyK0BItBSfXdSN1Z6ixRLymhZG3zWjbY= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5125A4BAE7D6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=simark.ca; s=mail; t=1773203233; bh=e73Y1hkGjR/vsBPb+qHxhG9tH5KStXnA3Ylj9EZSR90=; h=Date:Subject:To:References:From:In-Reply-To:From; b=bzH946UXKi7WPPxemQ+xobh2XCN9yBjIhZIcCnKLDVDr5RsegarQNpt0plcQx4V5E AuRu9ZfdvJFaXcPXZIKIhjT0tn2s1u49S6KLJbqCJj3v0kKdgiY2wojezpAywcsVTl 516qW/h/jaG0DWlZU6vYhMUCce8LiXMuJKnZz/pA= Received: by simark.ca (Postfix) id 9B5121E08D; Wed, 11 Mar 2026 00:27:12 -0400 (EDT) Message-ID: <6eb50919-75d8-4725-9afa-e241e4cabab6@simark.ca> Date: Wed, 11 Mar 2026 00:27:12 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [SH] Check FPSCR.PR for fldi0, fldi1 insns in simulator To: Oleg Endo , gdb-patches@sourceware.org References: <016918b6653a40835d2272c3c37d05b0d7e470b6.camel@gmail.com> Content-Language: en-US From: Simon Marchi In-Reply-To: <016918b6653a40835d2272c3c37d05b0d7e470b6.camel@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org On 2026-03-10 23:02, Oleg Endo wrote: > Hi, > > On SH variants with double-precision FPU the insns fli0 and flid1 require > that FPSCR.PR must be set to 0, i.e. single-precision mode. The attached > patch fixes that. > > OK to apply? > > Best regards, > Oleg Endo I looked for an ISA manual [1] and checked it for fun. For the FLID0, it says: When FPSCR.PR = 0, this instruction loads floating-point 0.0 (0x00000000) into FRn. Curiously, it does not say what happens if `FPSCR.PR = 1`. However, the description for FPSCR.PR says: PR: Precision mode PR = 0: Floating-point instructions are executed as single-precision operations. PR = 1: Floating-point instructions are executed as double-precision operations (the result of instructions for which double-precision is not supported is undefined). I guess that FLID0 and FLID1 fall into that "is undefined" category? Do you know what the real hardware does in this case? The patch LGTM, but I am not a maintainer of the sim, so: Reviewed-By: Simon Marchi One note, please put the relevant information (the body of your email) into the commit log itself). Thanks, Simon [1] https://0x04.net/~mwk/doc/sh/e602156_sh4.pdf