From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 116697 invoked by alias); 11 Jun 2018 02:44:34 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 116688 invoked by uid 89); 11 Jun 2018 02:44:33 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 spammy=lengths X-HELO: simark.ca Received: from simark.ca (HELO simark.ca) (158.69.221.121) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 11 Jun 2018 02:44:32 +0000 Received: from [10.0.0.11] (unknown [192.222.164.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by simark.ca (Postfix) with ESMTPSA id CC2A91E02D; Sun, 10 Jun 2018 22:44:30 -0400 (EDT) Subject: Re: [PATCH v2 09/10] Ptrace support for AArch64 SVE gdbsever To: Alan Hayward , gdb-patches@sourceware.org Cc: nd@arm.com References: <20180606151629.36602-1-alan.hayward@arm.com> <20180606151629.36602-10-alan.hayward@arm.com> From: Simon Marchi Message-ID: <6dd5d557-76dc-5c56-9471-03cd227d47d5@simark.ca> Date: Mon, 11 Jun 2018 02:44:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: <20180606151629.36602-10-alan.hayward@arm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-SW-Source: 2018-06/txt/msg00270.txt.bz2 On 2018-06-06 11:16 AM, Alan Hayward wrote: > diff --git a/gdb/gdbserver/linux-aarch64-low.c b/gdb/gdbserver/linux-aarch64-low.c > index 9db9a7c1c3..e7fec25a64 100644 > --- a/gdb/gdbserver/linux-aarch64-low.c > +++ b/gdb/gdbserver/linux-aarch64-low.c > @@ -73,6 +73,16 @@ is_64bit_tdesc (void) > return register_size (regcache->tdesc, 0) == 8; > } > > +static bool > +is_sve_tdesc (void) > +{ > + struct regcache *regcache = get_thread_regcache (current_thread, 0); > + > + /* Mimimum size of Z0 on SVE is 256bit. If not SVE, then Z0 will be the > + 128bit V0 register. */ > + return register_size (regcache->tdesc, AARCH64_SVE_Z0_REGNUM) >= 32; Hmm maybe I read wrong, but can't the SVE registers be 128 bits long? Maybe this is not up to date, but here it says "enabling implementation choices for vector lengths that scale from 128 to 2048 bits." https://community.arm.com/processors/b/blog/posts/technology-update-the-scalable-vector-extension-sve-for-the-armv8-a-architecture Simon