From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 31470 invoked by alias); 22 Feb 2010 22:07:45 -0000 Received: (qmail 31454 invoked by uid 22791); 22 Feb 2010 22:07:44 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL,BAYES_00,SARE_MSGID_LONG40 X-Spam-Check-By: sourceware.org Received: from mail-ew0-f223.google.com (HELO mail-ew0-f223.google.com) (209.85.219.223) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 22 Feb 2010 22:07:39 +0000 Received: by ewy23 with SMTP id 23so3469681ewy.4 for ; Mon, 22 Feb 2010 14:07:37 -0800 (PST) MIME-Version: 1.0 Received: by 10.216.157.149 with SMTP id o21mr2572797wek.4.1266876457109; Mon, 22 Feb 2010 14:07:37 -0800 (PST) In-Reply-To: <4B82FEE2.2090501@zytor.com> References: <20100218054312.GA9022@lucon.org> <6dc9ffc81002220757v5e9b48bdnba56a260f0f3c0a8@mail.gmail.com> <20100222161040.GD30100@caradoc.them.org> <201002221656.o1MGuw5q009795@glazunov.sibelius.xs4all.nl> <20100222170303.GG9493@caradoc.them.org> <201002221950.o1MJoomn007989@glazunov.sibelius.xs4all.nl> <6dc9ffc81002221306y6287491dv5aaac541ba303199@mail.gmail.com> <201002222130.o1MLU3ub013661@glazunov.sibelius.xs4all.nl> <6dc9ffc81002221341j735bdedeo7285951f4fc39c27@mail.gmail.com> <4B82FEE2.2090501@zytor.com> Date: Mon, 22 Feb 2010 22:07:00 -0000 Message-ID: <6dc9ffc81002221407w75999ffep82ef3b2e0feeb489@mail.gmail.com> Subject: Re: PATCH: Enable x86 XML target descriptions From: "H.J. Lu" To: "H. Peter Anvin" Cc: Mark Kettenis , dan@codesourcery.com, gdb-patches@sourceware.org, Suresh Siddha Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2010-02/txt/msg00562.txt.bz2 On Mon, Feb 22, 2010 at 2:02 PM, H. Peter Anvin wrote: > On 02/22/2010 01:41 PM, H.J. Lu wrote: >>>> >>>> Please see if my latest patch is OK: >>>> >>>> --- >>>> =A0/* Get CS register. =A0*/ >>>> =A0 errno =3D 0; >>>> =A0 cs =3D ptrace (PTRACE_PEEKUSER, tid, >>>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0offsetof (struct user_regs_struct, cs),= 0); >>>> =A0 if (errno !=3D 0) >>>> =A0 =A0 perror_with_name (_("Couldn't get CS register")); >>>> >>>> =A0 /* Value of CS register: >>>> =A0 =A0 =A01. 64bit: 0x33. >>>> =A0 =A0 =A02. 32bit: 0x23. >>>> =A0 =A0*/ >>>> =A0 if (cs =3D=3D 0x33) >>>> =A0 =A0 return tdesc_amd64_linux; >>>> =A0 else >>>> =A0 =A0 return tdesc_i386_linux; >>>> --- >>>> >>>> In kernel, there is >>>> >>>> =A0 =A0 =A0 regs->cs =3D test_thread_flag(TIF_64BIT_ILP32) ? __USER_CS= : __USER32_CS; >>> >>> I fear that's rather fragile. =A0I mean, the actual value of >>> __USER_CS/__USER32_CS is just an implementation detail isn't it? >>> >> >> That is how strace checks 32bit process on Linux/x86-64 =A0I have >> discussed it with Peter and Suresh. It is very unlikely Linux kernel will >> break strace. =A0In any case, =A0we will add a new ptrace option to Linux >> 2.6.35 to get TIF_64BIT_ILP32 among other things. I will update gdb >> to try the new ptrace option first and then fail back to CS register. >> > > Uhm... TIF_64BIT_ILP32 didn't go upstream (remember, we shut down that > project?) > > What I suggested was to add an strace option to get the segment > descriptor flags, which would include the CS.L bit for 64-bit mode. > Oops. Wrong kernel source. The idea is the same. It is the CS.L bit for 64-bit mode. That is /* Value of CS register: 1. 64bit: 0x33. 2. 32bit: 0x23. */ --=20 H.J.