From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id lAzdMVugFGSVaBIAWB0awg (envelope-from ) for ; Fri, 17 Mar 2023 13:16:11 -0400 Received: by simark.ca (Postfix, from userid 112) id C2CAC1E224; Fri, 17 Mar 2023 13:16:11 -0400 (EDT) Authentication-Results: simark.ca; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.a=rsa-sha256 header.s=default header.b=oRpD8SSN; dkim-atps=neutral X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,NICE_REPLY_A, RCVD_IN_DNSWL_HI,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 687901E222 for ; Fri, 17 Mar 2023 13:16:11 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8E95838515FF for ; Fri, 17 Mar 2023 17:16:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8E95838515FF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1679073370; bh=7nrpXddkHCW5vo32Uemp82jAOQlGpPnNhH7XZxnXyy0=; h=Date:Subject:To:Cc:References:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=oRpD8SSNS3lM0C5JcHeVX/v28Tvthg+J+pAC/g3PV3CAf5HKaVQLXYx58dIrZwF3z pv3qame+fKR4ieoJ+W/jGtU9OfAQ72hM7d2A1duZZFzgqVFfhZlUzpOMWUCQ8ajwyy K7fy+HEiVXtUtwODcQDHHld/ZjUbrRkDD175Drp4= Received: from simark.ca (simark.ca [158.69.221.121]) by sourceware.org (Postfix) with ESMTPS id 11F213858D28 for ; Fri, 17 Mar 2023 17:15:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 11F213858D28 Received: from [10.0.0.11] (unknown [217.28.27.60]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPSA id 01F1C1E0D3; Fri, 17 Mar 2023 13:15:49 -0400 (EDT) Message-ID: <6aa8edc2-81f7-b08a-805f-9a20185995d2@simark.ca> Date: Fri, 17 Mar 2023 13:15:49 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH] aarch64: Check for valid inferior thread/regcache before reading pauth registers Content-Language: en-US To: Luis Machado , Andrew Burgess , gdb-patches@sourceware.org, pedro@palves.net Cc: marcan@marcan.st References: <20230316103904.1947447-1-luis.machado@arm.com> <873564g0h3.fsf@redhat.com> <5ce96222-d665-5129-8d65-27c6933a6623@arm.com> In-Reply-To: <5ce96222-d665-5129-8d65-27c6933a6623@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Simon Marchi via Gdb-patches Reply-To: Simon Marchi Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" > ... despite the call to switch_to_no_thread in switch_to_inferior_no_thread from do_target_wait_1 > in the backtrace above, the call to ps_xfer_memory sets inferior_ptid momentarily before reading > memory: > > > static ps_err_e > ps_xfer_memory (const struct ps_prochandle *ph, psaddr_t addr, > gdb_byte *buf, size_t len, int write) > { > scoped_restore_current_inferior restore_inferior; > set_current_inferior (ph->thread->inf); > > scoped_restore_current_program_space restore_current_progspace; > set_current_program_space (ph->thread->inf->pspace); > > scoped_restore save_inferior_ptid = make_scoped_restore (&inferior_ptid); > inferior_ptid = ph->thread->ptid; > > CORE_ADDR core_addr = ps_addr_to_core_addr (addr); > > int ret; > if (write) > ret = target_write_memory (core_addr, buf, len); > else > ret = target_read_memory (core_addr, buf, len); > return (ret == 0 ? PS_OK : PS_ERR); > } > > > Maybe this shouldn't happen, or maybe it is just an unfortunate state to be in. But this > prevents the use of target_has_registers to guard against the lack of registers, since, > although current_thread_ is still nullptr, inferior_ptid is valid and is not null_ptid. It's needed to set inferior_ptid here because it's how we communicate to the targets which inferior / thread we want to read or write memory from. And we can't set current_thread_ to the the correponding thread_info *, because it does not exist at this point (we are in the process of creating it). And the problem is that aarch64_remove_non_address_bits assumes there is a current_thread_. Can we change aarch64_remove_non_address_bits to get the regcache using the ptid? get_thread_regcache (current_inferior ()->process_target (), inferior_ptid); Simon