From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 9401 invoked by alias); 2 Jul 2009 07:40:42 -0000 Received: (qmail 9377 invoked by uid 22791); 2 Jul 2009 07:40:38 -0000 X-SWARE-Spam-Status: No, hits=-1.1 required=5.0 tests=AWL,BAYES_00,J_CHICKENPOX_24,J_CHICKENPOX_25,J_CHICKENPOX_41,J_CHICKENPOX_53 X-Spam-Check-By: sourceware.org Received: from web112517.mail.gq1.yahoo.com (HELO web112517.mail.gq1.yahoo.com) (98.137.26.186) by sourceware.org (qpsmtpd/0.43rc1) with SMTP; Thu, 02 Jul 2009 07:40:30 +0000 Received: (qmail 52625 invoked by uid 60001); 2 Jul 2009 07:40:28 -0000 Message-ID: <630863.51520.qm@web112517.mail.gq1.yahoo.com> Received: from [123.237.137.145] by web112517.mail.gq1.yahoo.com via HTTP; Thu, 02 Jul 2009 00:40:28 PDT Date: Thu, 02 Jul 2009 07:40:00 -0000 From: paawan oza Subject: Re: i386.record.floating.point.patch : with more testing and assurity To: Hui Zhu , Pedro Alves , Mark Kettenis , Michael Snyder , gdb-patches@sourceware.org MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2009-07/txt/msg00055.txt.bz2 Hi, please ignore my previous mail regarding patch, some symbols were missing. I have incorporated the comments given by Hui.=20 please find the latest patch in the email body.=20 ------------ ChangeLog ----------- Current: gdb-6.8.50.20090531 2009-07-02 Oza * i386-tdep.c: Support for floating point recording. ------------ README ----------- Patch description: -> Provides floating point support for i386 (reversible debugging:record-r= eplay) -> previously gdb was not recording floating point registers, now all the f= loating point registers which are likely to be changed by floating point = instructions, are recorded and replayed. -> the patch intends to provide the full support for all i386 floating poin= t instructions. ----------------------------- test cases for the patch ---------------------------- #include #include #include /* the test intends to test following insns.=20=20 flds faddp fstps fstpl fldl fxch fabs fdivrp fmulp fsubrp fucomp fnstsw fsq= rt fchs f2xm1 fyl2x fxtract fprem1 fld fdecstp fld1 fldl2t fldl2e FLDPI FLDLG2= FLDLN2 FLDZ fincstp ffree fptan fpatan fincstp fsincos frndint fscale fsin fcos fc= movb fcmovbe fcmove fcmovu fcmovnb fcmovnbe fsave frstor fstsw=20 */ float no1,no2,no3,no4,no5,no6,no7; double x =3D 100.345, y =3D 25.7789; long double ldx =3D 88888888888888888888.88, ldy =3D 9999999999999999999.99; float result,resultd,resultld;=20 float *float_memory; /* initialization of floats */ void init_floats() { no1 =3D 10.45; no2 =3D 20.77; no3 =3D 156.89874646; no4 =3D 14.56; no5 =3D 11.11; no6 =3D 66.77; no7 =3D 88.88; float_memory =3D malloc(sizeof(float) * 4); *float_memory =3D 256.256; *(float_memory + 1) =3D 356.356; *(float_memory + 2) =3D 456.456; *(float_memory + 3) =3D 556.556; } /* marks FPU stack as empty */ void empty_fpu_stack() { asm ("ffree %st(1) \n\t" "ffree %st(2) \n\t" "ffree %st(3) \n\t" "ffree %st(4) \n\t" "ffree %st(5) \n\t" "ffree %st(6) \n\t" "ffree %st(7)"); }=20=20=20 /* tests floating point arithmatic */ void test_arith_floats() { result =3D no1 + no2 + no3 + no4 + no5 + no6 + no7; printf("result is %f\n",result); result =3D fmodf(no2,no1);=20 printf("result is %f\n",result); resultd =3D fmod(x,y);=20 printf("result is %f\n",resultd); resultld =3D fmodl(ldy,ldy);=20 printf("result is %f\n",resultld); result =3D fabsf(no1);=20=20=20=20=20=20=20=20 printf("result is %f\n",result); result =3D no3 / no4; printf("result is %f\n",result); result =3D no1 * no2 * no3 * no4; printf("result is %f\n",result); result =3D no1 - no2 - no3 - no4; printf("result is %f\n",result); asm ("fld %0" : :"m"(*float_memory)); asm ("fchs"); =20=20 /* test for f2xm1 */=20=20 asm ("fld %0" : :"m"(*float_memory));=20 asm ("f2xm1"); asm ("fyl2x"); asm ("fld %0" : :"m"(*float_memory));=20 asm ("fxtract"); asm ("fld %0" : :"m"(*float_memory));=20 asm ("fprem1"); /* decrement fpu stack pointer only status register should get affected */ asm ("fld %0" : :"m"(*float_memory));=20=20=20 =20=20 empty_fpu_stack(); =20=20 asm ("fld1"); asm ("fldl2t"); asm ("fldl2e"); asm ("fldpi"); asm ("fldlg2"); asm ("fldln2"); asm ("fldz"); empty_fpu_stack(); /* finishing emptying the stack */ =20=20=20=20=20=20 result =3D sqrt(no3); printf("result is %f\n",result); } void test_log_exp_floats() { result =3D log10(no3); printf("result is %f\n",result); result =3D log(no3); printf("result is %f\n",result); result =3D exp10(no3); printf("result is %f\n",result); result =3D exp(no3); printf("result is %f\n",result); } void test_trigo_floats() { result =3D sin(30); printf("result is %f\n",result); result =3D cos(30); printf("result is %f\n",result); result =3D tan(30); printf("result is %f\n",result); result =3D atan(30); printf("result is %f\n",result); asm ("fld %0" : :"m"(*float_memory));=20 asm ("fptan"); /* changes st1 and popping register stack */ asm ("fpatan");=20=20 asm("fincstp"); asm ("fld %0" : :"m"(float_memory));=20 asm ("fsincos"); asm ("fld %0" : :"m"(*float_memory));=20 asm ("frndint"); asm ("fld %0" : :"m"(*float_memory)); asm ("fld %0" : :"m"(*(float_memory+1)));=20=20 asm ("fscale"); empty_fpu_stack(); asm ("fld %0" : :"m"(*float_memory));=20 asm ("fsin"); asm ("fcos"); /* currently we assume condition likely and always record the registers=20 code could be optimized only if the flag is set then record */ asm ("fld %0" : :"m"(*float_memory)); asm ("fld %0" : :"m"(*(float_memory+1)));=20=20 asm ("fcmovb %st(1), %st"); asm ("fcmovbe %st(1), %st"); asm ("fcmove %st(1), %st"); asm ("fcmovu %st(1), %st"); asm ("fcmovnb %st(1), %st"); asm ("fcmovnbe %st(1), %st"); empty_fpu_stack(); /* finished emtyping the stack */ } void test_compare_floats() { ldy =3D 88888888888888888888.88; if (ldx =3D=3D ldy) ldy =3D 7777777777777777777777777777.777; else ldy =3D 666666666666666666666666666.666; } /* test loading and saving of FPU environment */ void test_fpu_env() { asm ("fsave %0" : "=3Dm"(*float_memory) : ); asm ("frstor %0" : : "m"(*float_memory)); asm ("fstsw %ax");=20=20 } int main() { init_floats(); test_arith_floats(); test_log_exp_floats(); test_trigo_floats(); test_compare_floats(); test_fpu_env(); } ------------------------ i386.floats.prec.patch ------------------------- diff -urN gdb.orig/i386-tdep.c gdb.new/i386-tdep.c --- gdb.orig/i386-tdep.c 2009-05-29 17:08:40.000000000 -0400 +++ gdb.new/i386-tdep.c 2009-07-02 12:56:56.000000000 -0400 @@ -543,6 +543,9 @@ /* The maximum number of saved registers. This should include all registers mentioned above, and %eip. */ #define I386_NUM_SAVED_REGS I386_NUM_GREGS +#define I386_SAVE_FPU_REGS 0xFFFD +#define I386_SAVE_FPU_ENV 0xFFFE +#define I386_SAVE_FPU_ENV_REG_STACK 0xFFFF =20 struct i386_frame_cache { @@ -2985,6 +2988,55 @@ return 0; } =20 +/* Record the value of floating point registers which will be changed by t= he current instruction + to "record_arch_list". + return -1 if something is wrong. */=20=20 + +static int i386_record_floats(struct i386_record_s *ir, uint32_t iregnum) +{ + int i; + + /* Oza : push/pop of fpu stack is going to happen=20 + currently we store st0-st7 registers, but we need not store all regis= ters all the time. + using fstatus, we use 11-13 bits which gives us stack top and hence w= e optimize our storage. + alternatively we can use ftag register too */ + if (I386_SAVE_FPU_REGS =3D=3D iregnum) + { + for (i=3DI386_ST0_REGNUM;i<=3DI386_ST0_REGNUM+7;i++) + { + if (record_arch_list_add_reg (ir->regcache,i)) + return -1;=20=20=20=20 + } + } + else if (I386_SAVE_FPU_ENV =3D=3D iregnum) + { + for (i=3DI386_ST0_REGNUM+8;i<=3DI386_ST0_REGNUM+15;i++) + { + if (record_arch_list_add_reg (ir->regcache,i)) + return -1;=20=20=20=20 + } + } + else if (I386_SAVE_FPU_ENV_REG_STACK =3D=3D iregnum) + { + for (i=3DI386_ST0_REGNUM;i<=3DI386_ST0_REGNUM+15;i++) + { + if (record_arch_list_add_reg (ir->regcache,i)) + return -1;=20=20=20=20 + } + } + else if (iregnum >=3D I386_ST0_REGNUM && iregnum <=3D I386_ST0_REGNUM+15) + { + if (record_arch_list_add_reg (ir->regcache,iregnum)) + return -1; + } + else + { + /* param Error */ + return -1; + }=20 + return 0; +} + /* Parse the current instruction and record the values of the registers and memory that will be changed in current instruction to "record_arch_list= ". Return -1 if something wrong. */ @@ -4035,7 +4087,6 @@ break; =20 /* floats */ - /* It just record the memory change of instrcution. */ case 0xd8: case 0xd9: case 0xda: @@ -4056,39 +4107,49 @@ return -1; switch (ir.reg) { - case 0x00: - case 0x01: case 0x02: - case 0x03: + case 0x12: + case 0x22: + case 0x32: + /* for FCOM, FICOM nothing to do */ + break; + case 0x03: + case 0x13: + case 0x23: + case 0x33: + /* FCOMP, FICOMP pop FPU stack, store all */ + if (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) + return -1; + break; + case 0x00: + case 0x01: case 0x04: case 0x05: case 0x06: case 0x07: case 0x10: - case 0x11: - case 0x12: - case 0x13: + case 0x11: case 0x14: case 0x15: case 0x16: case 0x17: case 0x20: case 0x21: - case 0x22: - case 0x23: case 0x24: case 0x25: case 0x26: case 0x27: case 0x30: case 0x31: - case 0x32: - case 0x33: case 0x34: case 0x35: case 0x36: case 0x37: - break; + /* FADD, FMUL, FSUB, FSUBR, FDIV, FDIVR, FIADD, FIMUL, FISUB, FISUB= R, FIDIV, FIDIVR=20=20 + ModR/M.reg is an extension of code, always affects st(0) reg= ister */ + if (i386_record_floats(&ir, I386_ST0_REGNUM)) + return -1; + break;=20=20=20=20=20=20=20=20=20=20=20=09=20=20=20=20=09=20= =20=20=20 case 0x08: case 0x0a: case 0x0b: @@ -4096,6 +4157,7 @@ case 0x19: case 0x1a: case 0x1b: + case 0x1d:=20 case 0x28: case 0x29: case 0x2a: @@ -4103,11 +4165,16 @@ case 0x38: case 0x39: case 0x3a: - case 0x3b: + case 0x3b:=09=20=20=20 + case 0x3c:=20 + case 0x3d:=20 switch (ir.reg & 7) { case 0: - break; + /* FLD, FILD */ + if (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) + return -1;=20=20=20=20 + break; case 1: switch (ir.reg >> 4) { @@ -4120,6 +4187,7 @@ return -1; break; case 3: + break; default: if (record_arch_list_add_mem (addr, 2)) return -1; @@ -4130,15 +4198,42 @@ switch (ir.reg >> 4) { case 0: + if (record_arch_list_add_mem (addr, 4)) + return -1; + if (3 =3D=3D (ir.reg & 7)) + { + /* FSTP m32fp */ + if (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) + return -1;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20 + }=20 + break; case 1: if (record_arch_list_add_mem (addr, 4)) return -1; + if ((3 =3D=3D (ir.reg & 7)) || (5 =3D=3D (ir.reg & 7)) || (7 =3D= =3D (ir.reg & 7))) + { + /* FSTP */ + if (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) + return -1;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20 + }=20 break; case 2: if (record_arch_list_add_mem (addr, 8)) return -1; + if (3 =3D=3D (ir.reg & 7)) + { + /* FSTP m64fp */ + if (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) + return -1;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20 + }=20 break; case 3: + if ((3 <=3D (ir.reg & 7)) && (6 <=3D (ir.reg & 7))) + { + /* FISTP, FBLD, FILD, FBSTP */ + if (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) + return -1;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20 + }=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20 default: if (record_arch_list_add_mem (addr, 2)) return -1; @@ -4147,54 +4242,71 @@ break; } break; - case 0x0c: - case 0x0d: - case 0x1d: - case 0x2c: - case 0x3c: - case 0x3d: - break; - case 0x0e: + case 0x0c: + /* FLDENV */ + if (i386_record_floats(&ir, I386_SAVE_FPU_ENV_REG_STACK)) + return -1;=20=20 + break; + case 0x0d:=20 + /* FLDCW */ + if (i386_record_floats(&ir, I386_ST0_REGNUM + 8)) + return -1;=20=20 + break; + case 0x2c:=20 + /* FRTSTOR */ + if (i386_record_floats(&ir, I386_SAVE_FPU_ENV_REG_STACK)) + return -1;=20=20 + break;=20 + case 0x0e:=20 if (ir.dflag) { - if (record_arch_list_add_mem (addr, 28)) - return -1; + if (record_arch_list_add_mem (addr, 28)) + return -1; } else { - if (record_arch_list_add_mem (addr, 14)) - return -1; + if (record_arch_list_add_mem (addr, 14)) + return -1; } break; - case 0x0f: - case 0x2f: + case 0x0f:=20=20 + case 0x2f:=20=20 if (record_arch_list_add_mem (addr, 2)) return -1; break; - case 0x1f: - case 0x3e: + case 0x1f:=20=20 + case 0x3e:=20=20 if (record_arch_list_add_mem (addr, 10)) return -1; + /* FSTP, FBSTP */ + if (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) + return -1;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 break; - case 0x2e: + case 0x2e:=20 if (ir.dflag) { - if (record_arch_list_add_mem (addr, 28)) - return -1; - addr +=3D 28; + if (record_arch_list_add_mem (addr, 28)) + return -1; + addr +=3D 28; } else { - if (record_arch_list_add_mem (addr, 14)) - return -1; - addr +=3D 14; + if (record_arch_list_add_mem (addr, 14)) + return -1; + addr +=3D 14; } if (record_arch_list_add_mem (addr, 80)) return -1; + /* FSAVE */ + if (i386_record_floats(&ir, I386_SAVE_FPU_ENV_REG_STACK)) + return -1;=20=20=20 break; - case 0x3f: + case 0x3f:=20 if (record_arch_list_add_mem (addr, 8)) return -1; + /* FISTP */ + if (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) + return -1;=20=20=20 break; default: ir.addr -=3D 2; @@ -4202,9 +4314,180 @@ goto no_support; break; } - } + }=20=20=20 + /* opcode is an extension of modR/M byte */=20=20=20=20=20 + else + {=20 + switch (opcode) + { + case 0xd8: + if (i386_record_floats(&ir, I386_ST0_REGNUM)) + return -1;=09 + break; + case 0xd9:=20=20=20=20 + if (0x0c =3D=3D (ir.modrm >> 4)) + { + if ((ir.modrm & 0x0f) <=3D 7) + { + if (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) + return -1;=09 + } + else + { + if (i386_record_floats(&ir, I386_ST0_REGNUM)) + return -1;=09 + /* if only st(0) is changing, then we have already rec= orded */ + if ((ir.modrm & 0x0f) - 0x08) + { + if (i386_record_floats(&ir, I386_ST0_REGNUM + ((ir.m= odrm & 0x0f) - 0x08))) + return -1;=09=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20 + }=20 + }=20=20 + } + else + { + switch(ir.modrm) + { + case 0xe0: + case 0xe1: + case 0xf0: + case 0xf5: + case 0xf8: + case 0xfa: + case 0xfc: + case 0xfe: + case 0xff: + if (i386_record_floats(&ir, I386_ST0_REGNUM)) + return -1; + break;=20=20=20=20=20=20=20=20=20=20=20 + case 0xf1:=20=20 + case 0xf2:=20=20 + case 0xf3:=20=20 + case 0xf4: + case 0xf6:=20 + case 0xf7:=20=20=20=20 + case 0xe8:=20=20 + case 0xe9:=20=20 + case 0xea:=20=20 + case 0xeb: + case 0xec:=20=20=20=20=20=20=20=20 + case 0xed:=20=20=20=20 + case 0xee:=20=20=20 + case 0xf9:=20=20=20=20=20 + case 0xfb: + if (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) + return -1;=09 + break; + case 0xfd:=20 + if (i386_record_floats(&ir, I386_ST0_REGNUM)) + return -1; + if (i386_record_floats(&ir, I386_ST0_REGNUM + 1)) + return -1; + break; + }=20 + } + break; + case 0xda: + if (0xe9 =3D=3D ir.modrm) + { + if (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) + return -1;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20 + } + else if ((0x0c =3D=3D ir.modrm >> 4) || (0x0d =3D=3D ir.modr= m >> 4)) + { + if (i386_record_floats(&ir, I386_ST0_REGNUM)) + return -1;=09=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20 + if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <=3D 7)) + { + if (i386_record_floats(&ir, I386_ST0_REGNUM + (ir.modrm = & 0x0f))) + return -1;=09=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20 + } + else if ((ir.modrm & 0x0f) - 0x08) + { + if (i386_record_floats(&ir, I386_ST0_REGNUM + ((ir.modrm & 0x0f) - 0x0= 8))) + return -1; + } + }=20=20 + break;=20 + case 0xdb: + if (0xe3 =3D=3D ir.modrm) + { + if (i386_record_floats(&ir, I386_SAVE_FPU_ENV)) + return -1;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20 + } + else if ((0x0c =3D=3D ir.modrm >> 4) || (0x0d =3D=3D ir.modr= m >> 4)) + { + if (i386_record_floats(&ir, I386_ST0_REGNUM)) + return -1;=09=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20 + if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <=3D 7)) + { + if (i386_record_floats(&ir, I386_ST0_REGNUM + (ir.modrm = & 0x0f))) + return -1;=09=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20 + } + else if ((ir.modrm & 0x0f) - 0x08) + { + if (i386_record_floats(&ir, I386_ST0_REGNUM + ((ir.modrm & 0x0f) - 0x0= 8))) + return -1; + } + }=20=20 + break; + case 0xdc: + if ((0x0c =3D=3D ir.modrm >> 4) || (0x0d =3D=3D ir.modrm >> = 4) || (0x0f =3D=3D ir.modrm >> 4)) + { + if ((ir.modrm & 0x0f) <=3D 7) + { + if (i386_record_floats(&ir, I386_ST0_REGNUM + (ir.modrm = & 0x0f))) + return -1;=09=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20 + } + else + { + if (i386_record_floats(&ir, I386_ST0_REGNUM + ((ir.modrm & 0x0f) - 0x0= 8))) + return -1; + } + }=20=20 + break; + case 0xdd:=20=20=20=20=20=20=20=20=20=20=20=20=20 + if (0x0c =3D=3D ir.modrm >> 4) + { + if (i386_record_floats(&ir,I386_ST0_REGNUM + 10)) + return -1; + } + else if ((0x0d =3D=3D ir.modrm >> 4) || (0x0e =3D=3D ir.modr= m >> 4)) + {=20 + if ((ir.modrm & 0x0f) <=3D 7) + { + if (i386_record_floats(&ir, I386_ST0_REGNUM + (ir.mo= drm & 0x0f))) + return -1;=09=20 + } + else + { + if (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) + return -1; + } + }=20=20=20=20=20=20=20=20=20=20=20=20 + break; + case 0xde: + if ((0x0c =3D=3D ir.modrm >> 4) || (0x0e =3D=3D ir.modrm >> = 4) || (0x0f =3D=3D ir.modrm >> 4) || (0xd9 =3D=3D ir.modrm)) + {=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 + if (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) + return -1;=09=20 + }=20=20=20 + break; + case 0xdf: + if (0xe0 =3D=3D ir.modrm) + { + if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGN= UM)) + return -1; + } + else if ((0x0f =3D=3D ir.modrm >> 4) || (0x0e =3D=3D ir.modr= m >> 4)) + {=20 + if (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) + return -1; + }=20 + break; + }=20=09=20=20 + }=20=20=20=20=20=20=20=20=20 break; - /* string ops */ /* movsS */ case 0xa4: @@ -4623,10 +4906,17 @@ /* fwait */ /* XXX */ case 0x9b: - printf_unfiltered (_("Process record doesn't support instruction " - "fwait.\n")); - ir.addr -=3D 1; - goto no_support; + if (target_read_memory (ir.addr, &tmpu8, 1)) + { + if (record_debug) + printf_unfiltered (_("Process record: error reading memory at " + "addr 0x%s len =3D 1.\n"), + paddr_nz (ir.addr)); + return -1; + } + opcode =3D (uint32_t) tmpu8; + ir.addr++; + goto reswitch;=20=20=20=20=20 break; =20 /* int3 */ --- On Thu, 7/2/09, Hui Zhu wrote: > From: Hui Zhu > Subject: Re: i386.record.floating.point.patch : with more testing and ass= urity > To: "paawan oza" > Cc: "Pedro Alves" , "Mark Kettenis" , "Michael Snyder" , gdb-patches@sourceware= .org > Date: Thursday, July 2, 2009, 7:31 AM > On Wed, Jul 1, 2009 at 23:59, paawan > oza > wrote: > > > > Hi Hui, > > > > As I clarified earlier, > > these registers are already supported and extended by > gdb much before this patch. > > all floating point registers are already supported by > gdb > > (info floats/info all-registers command gives it) > > > > My aim is : only to make sure that whenever any > floating point insn gets executed, we record the registers > > (no matter whether it is %st(n) or FCTRL or FTAG or > FSTATUS) > > there are insns > > e.g. 'ffree' changes FTAG register, so we must record > it. > > > > Do you mean to say that we should remove it from just > enumaration ? > > but anyway we need to record those registers. > > >=20 > You are working on make prec x86 support fp insn, not to > extend the fp > function of i386 (If you want, you can make a special patch > for it). >=20 >=20 >=20 >=20 > > > > --- On Wed, 7/1/09, Hui Zhu > wrote: > > > >> From: Hui Zhu > >> Subject: Re: i386.record.floating.point.patch : > with more testing and assurity > >> To: "paawan oza" , > "Pedro Alves" , > "Mark Kettenis" , > "Michael Snyder" > >> Cc: gdb-patches@sourceware.org > >> Date: Wednesday, July 1, 2009, 11:23 AM > >> About this patch, I say my idea > >> again, I told in > >> http://sourceware.org/ml/gdb-patches/2009-06/msg00014.html > >> @@ -145,7 +145,22 @@ > >> =A0=A0=A0I386_ES_REGNUM, > >> =A0=A0=A0 /* %es */ > >> =A0=A0=A0I386_FS_REGNUM, > >> =A0=A0=A0 /* %fs */ > >> =A0=A0=A0I386_GS_REGNUM, > >> =A0=A0=A0 /* %gs */ > >> -=A0 I386_ST0_REGNUM > >> =A0=A0=A0 /* %st(0) */ > >> +=A0 I386_ST0_REGNUM, > >> =A0=A0=A0 /* %st(0) */ > >> +=A0 I386_ST1_REGNUM, > >> =A0=A0=A0 /* %st(1) */ > >> +=A0 I386_ST2_REGNUM, > >> =A0=A0=A0 /* %st(2) */ > >> +=A0 I386_ST3_REGNUM, > >> =A0=A0=A0 /* %st(3) */ > >> +=A0 I386_ST4_REGNUM, > >> =A0=A0=A0 /* %st(4) */ > >> +=A0 I386_ST5_REGNUM, > >> =A0=A0=A0 /* %st(5) */ > >> +=A0 I386_ST6_REGNUM, > >> =A0=A0=A0 /* %st(6) */ > >> +=A0 I386_ST7_REGNUM, > >> =A0=A0=A0 /* %st(7) */ > >> +=A0 I386_FCTRL, > >> =A0=A0=A0 /* floating point env regs : FCTRL-FOP > >> */ > >> +=A0 I386_FSTAT, > >> +=A0 I386_FTAG, > >> > >> +=A0 I386_FISEG, > >> +=A0 I386_FIOFF, > >> +=A0 I386_FOSEG, > >> +=A0 I386_FOOFF, > >> +=A0 I386_FOP > >> =A0}; > >> > >> You are working on make prec x86 support fp insn, > not to > >> extend the fp > >> function of i386 (If you want, you can make a > special patch > >> for it). > >> > >> Hui > >> > >> On Tue, Jun 30, 2009 at 23:05, paawan oza > >> wrote: > >> > > >> > Hi, > >> > As I am submitting the patch for the first > time, I am > >> not much aware of gdb test suite. > >> > would you please guide me about how I can put > the > >> things in the testsuite ? > >> > is it the testsuite which comes along with > the gdb > >> source ? > >> > gdb\testsuite\gdb.base ?? > >> > Regards, > >> > Oza. > >> > > >> > --- On Tue, 6/30/09, Pedro Alves > >> wrote: > >> > > >> >> From: Pedro Alves > >> >> Subject: Re: > i386.record.floating.point.patch : > >> with more testing and assurity > >> >> To: gdb-patches@sourceware.org > >> >> Cc: "paawan oza" , > >> teawater@gmail.com > >> >> Date: Tuesday, June 30, 2009, 7:09 PM > >> >> On Tuesday 30 June 2009 14:23:30, > >> >> paawan oza wrote: > >> >> > > >> >> > > As suggested by Hui, > >> >> > > I have come up with more > detailed and > >> granular > >> >> test case > >> >> > > for the patch which I had > submitted last > >> week. > >> >> > >> >> Could you please consider migrating that > test into > >> the > >> >> testsuite? > >> >> You've gone through the trouble of > writing tests > >> to make > >> >> sure > >> >> the features work now --- putting it in > the > >> testsuite means > >> >> we > >> >> have an automatic-ish means to check that > it > >> doesn't get > >> >> inadvertently broken in the future.=A0 The > way it > >> is, > >> >> when your > >> >> code gets in, the test will probably end > up lost > >> in the > >> >> archives. > >> >> We wouldn't want that, would we?=A0 :-)=A0 > Having > >> >> auto-tests, also helps > >> >> the person doing the review in confirming > things > >> work as > >> >> expected (without much effort). > >> >> > >> >> -- > >> >> Pedro Alves > >> >> > >> > > >> > > >> > > >> > > >> > > > > > > > > >=20