From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 81411 invoked by alias); 18 Mar 2016 15:03:37 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 81388 invoked by uid 89); 18 Mar 2016 15:03:36 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD,SPF_HELO_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Fri, 18 Mar 2016 15:03:26 +0000 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (Postfix) with ESMTPS id A5A031F57B; Fri, 18 Mar 2016 15:03:25 +0000 (UTC) Received: from [127.0.0.1] (ovpn01.gateway.prod.ext.phx2.redhat.com [10.5.9.1]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u2IF3OOQ013402; Fri, 18 Mar 2016 11:03:25 -0400 Subject: Re: [PATCH 4/8] Force to insert software single step breakpoint To: Yao Qi References: <1457088276-1170-1-git-send-email-yao.qi@linaro.org> <1457088276-1170-5-git-send-email-yao.qi@linaro.org> <56E2B0C2.705@redhat.com> <86egbay78l.fsf@gmail.com> <56EAA5A4.5040601@redhat.com> <86shznx3rd.fsf@gmail.com> Cc: gdb-patches@sourceware.org From: Pedro Alves Message-ID: <56EC18BC.9050404@redhat.com> Date: Fri, 18 Mar 2016 15:03:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <86shznx3rd.fsf@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-SW-Source: 2016-03/txt/msg00339.txt.bz2 On 03/18/2016 02:24 PM, Yao Qi wrote: > Pedro Alves writes: > >> Maybe what we need to do is firmly declare (and add comments in that >> direction) that the arch's get_next_pcs implementation must always evaluate >> the condition of conditional branches, and not put a breakpoint at the >> branch destination if the condition is false, thus ensuring forward progress. >> The ARM implementation does this, though I haven't checked whether all the >> branch instructions are covered. Some other archs don't, and always put >> a break at the branch destination, like e.g., moxie_software_single_step. > > Some targets doesn't evaluate condition and simply insert breakpoint on > possible destinations. They are cris, moxie, sparc and spu. I'll add > condition evaluation to these software single step implementations. > Hmm, that is more work than I'd imagine you'd do. I wasn't really thinking you'd go hack those ports. I'd be content with just adding the comment, and leaving the ports be, being happy that we know about a path forward if necessary. I think before my software single-step rework, these archs may already have had this issue, as I think old gdb would insert the software single-step breakpoint in this scenario. We may not see it happen in practice on those archs, as I think usually spinlock-style asm needs at least two instructions; one to load from an address, another to conditionally branch. >> >> If we find some instruction where that is still not be sufficient, >> due to side effects, then maybe gdb and gdbserver could first >> try emulating the instruction's side effects manually. And only >> if that doesn't work, then try displaced stepping. We could leave >> that for later, until we find a need. > > What does "that" mean in "We could leave that for later"? Is it > "instruction emulation + displaced stepping" or "displaced stepping"? The whole "instruction emulation + displaced stepping". > It is difficult to do instruction emulation for these targets, because I > need to understand the details all these targets. Just make sure I > correctly understand the scope of the work. Thanks, Pedro Alves