From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 128292 invoked by alias); 5 Feb 2016 11:29:30 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 127460 invoked by uid 89); 5 Feb 2016 11:29:28 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=4095, straightforward, annoyance, hopes X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 05 Feb 2016 11:29:27 +0000 Received: from svr-orw-fem-04.mgc.mentorg.com ([147.34.97.41]) by relay1.mentorg.com with esmtp id 1aReZn-00000C-Ec from Luis_Gustavo@mentor.com ; Fri, 05 Feb 2016 03:29:23 -0800 Received: from [172.30.8.237] (147.34.91.1) by svr-orw-fem-04.mgc.mentorg.com (147.34.97.41) with Microsoft SMTP Server id 14.3.224.2; Fri, 5 Feb 2016 03:29:23 -0800 Reply-To: Luis Machado Subject: Re: [PATCH] Handle loading improper core files gracefully in the mips backend. References: <1452277948-25292-1-git-send-email-lgustavo@codesourcery.com> <5693CE90.1060709@codesourcery.com> <5694F5BC.3050904@redhat.com> <5694FEB8.10406@codesourcery.com> <56950952.2030504@redhat.com> <56951F29.7070000@codesourcery.com> <56B0A809.6070101@codesourcery.com> <56B0BAEA.7@redhat.com> <56B0BBB4.6050105@redhat.com> To: "Maciej W. Rozycki" , Pedro Alves CC: , Jan Kratochvil From: Luis Machado Message-ID: <56B4878F.2000201@codesourcery.com> Date: Fri, 05 Feb 2016 11:29:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2016-02/txt/msg00137.txt.bz2 On 02/04/2016 07:01 PM, Maciej W. Rozycki wrote: > On Tue, 2 Feb 2016, Pedro Alves wrote: > >>> Did you try to trigger the assertion by loading a 32-bit MIPS binary >>> into gdb, and playing with "set mips abi n64/o64...", "set mipsfpu", >>> etc? >>> >>> I think that adding a test to the testsuite that iterates through all >>> the possible combinations just to make sure gdb doesn't crash >>> would be great, and also show that the patch stands on its own >>> as well, irrespective of the bfd arch compatibility issues. I was playing around with these settings. >> >> TBC, I meant, the original patch that checked unsuitable ABI/ISA >> combinations. > > NB I can only see the use for these knobs to deal with two situations: > > 1. There's no executable and we want to connect to a live target for > minimal binary-only/disasembly-level debugging. We need to set the > endianness, ABI, ISA, etc. to match the target then (although arguably > at least the endianness should be supplied by the debug stub somehow; > we just don't have a way defined right now). > While trying reproducers out, i noticed this use case doesn't seem to work properly under some conditions anymore. Whenever GDB doesn't find a binary and sysroot is set to empty, it will not attempt to continue with the remote session. It seems to just give up. Sending packet: $qXfer:exec-file:read:6394:0,fff#60...Packet received: lgdb.base/break <- remote->to_xfer_partial (0xcb3a80, 27, 6394, 0xe38cc0, 0x0, 0x0, 0xfff, 0x98) = 1 remote:target_xfer_partial (27, 6394, 0xe38cc0, 0x0, 0x0, 4095) = 1, 152, bytes = 2f 6e 65 74 2f 62 75 69 6c 64 32 2d 6c 75 63 69 ... -> remote->to_check_pending_interrupt (...) <- remote->to_check_pending_interrupt (0xcb3a80) -> remote->to_xfer_partial (...) <- remote->to_xfer_partial (0xcb3a80, 27, 6394, 0xe38d58, 0x0, 0x98, 0xf67, 0x0) = 0 remote:target_xfer_partial (27, 6394, 0xe38d58, 0x0, 0x98, 3943) = 0, 0 <- remote->to_pid_to_exec_file (0xcb3a80, 25492) = gdb.base/break target_close () gdb.base/break: No such file or directory. (gdb) i r The program has no registers now. (gdb) kill The program is not being run. Otherwise gdbserver will transfer the file over from the remote end. But i digress. I can easily reproduce the internal error by simply loading a 32-bit MIPS binary and flipping the abi to any of the 64-bit variants. This doesn't seem to be terribly important as people interested in playing with these setting will most likely know what they're doing. The testcase causing an internal error seems to be even less important and very unlikely to occur, but it always runs as part of the testsuite and it is a bit of an annoyance. GDB should not give an internal error or crash, obviously. > 2. We have a buggy or outdated GDB executable which fails to determine the > right settings automatically. As it looks for example as recently as > last week I came across a problem where GDB failed to detect the > presence of the FPU under Linux for some reason. I had to forcefully > request `set mipsfpu double' to override the wrongly chosen setting of > `none', at which point accesses to the FPU worked as expected, so it > wasn't like the unit was inaccessible. > > Obviously I need to debug #2, but overall I agree we ought to bail out > gracefully rather than crash if the manual settings lead to a nonsensical > configuration. > > Therefore I went back to the original patch now. It obscures things a > bit I'm afraid from my point of view as it combines a syntactical change > (the addition of the `arch_is_incompatible' auxiliary variable) and a > semantical change (the addition of the `mips_isa == ISA_MIPS16' check), so > I'd like to see the two changes separated. > > TBH I'm not convinced whether the auxiliary variable buys us anything > here -- it doesn't serve as documentation as we have an explanatory > comment here already, which BTW needs to be updated accordingly if the > condition is extended to cover an ISA incompatibility. The naming could've been better. I went that route in the hopes that future checks would just flip that boolean while keeping the conditional block separate, otherwise we would have a bigger conditional block that may not be as straightforward to parse. > > As to which, and more importantly -- there is no actual architectural > incompatibility between the n64 (or n32) ABI and the MIPS16 instruction > set; there are 64-bit MIPS processors in existence which implement the > MIPS16 ISA as well, e.g. the NEC VR4111, and the ISA itself includes > 64-bit instructions on such a processor. So the MIPS16 ISA is really > agnostic to the ABI, just as is the regular MIPS ISA or the microMIPS ISA. > Therefore any such fix needs to go elsewhere I'm afraid -- we probably do > something outright silly for the ISA_MIPS16 setting. Fair enough. Do you have a suggestion on where that fix should go to? The culprit seems to be the mix of an arch selection that gives us 64-bit cooked registers (due to mips_abi_regsize) and an ISA that gives us 32-bit registers (due to mips_isa_regsize). With that combination, mips_pseudo_register_read will fail in a fatal way, as well as mips_pseudo_register_write if we ever manage to go past the reading step. Luis