From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 114437 invoked by alias); 13 Jan 2016 19:10:22 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 114423 invoked by uid 89); 13 Jan 2016 19:10:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY autolearn=no version=3.3.2 spammy=you!, you X-HELO: usplmg20.ericsson.net Received: from usplmg20.ericsson.net (HELO usplmg20.ericsson.net) (198.24.6.45) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Wed, 13 Jan 2016 19:10:20 +0000 Received: from EUSAAHC008.ericsson.se (Unknown_Domain [147.117.188.96]) by usplmg20.ericsson.net (Symantec Mail Security) with SMTP id 52.16.06940.3FE96965; Wed, 13 Jan 2016 20:01:08 +0100 (CET) Received: from [153.88.4.164] (147.117.188.8) by smtp-am.internal.ericsson.com (147.117.188.98) with Microsoft SMTP Server id 14.3.248.2; Wed, 13 Jan 2016 14:10:17 -0500 Subject: Re: [PATCH v8 5/7] Support software single step on ARM in GDBServer To: Yao Qi References: <1450361684-29536-1-git-send-email-antoine.tremblay@ericsson.com> <1450361684-29536-6-git-send-email-antoine.tremblay@ericsson.com> <86io2xv4oj.fsf@gmail.com> CC: From: Antoine Tremblay Message-ID: <5696A115.3070703@ericsson.com> Date: Wed, 13 Jan 2016 19:10:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Icedove/38.4.0 MIME-Version: 1.0 In-Reply-To: <86io2xv4oj.fsf@gmail.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2016-01/txt/msg00272.txt.bz2 On 01/13/2016 11:13 AM, Yao Qi wrote: > Antoine Tremblay writes: > >> + >> +/* Get the raw next possible addresses. PC in next_pcs is the current program >> + counter, which is assumed to be executing in ARM mode. >> + >> + The values returned have the execution state of the next instruction >> + encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is >> + in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory >> + address in GDB and arm_addr_bits_remove in GDBServer. */ >> + >> +VEC (CORE_ADDR) * >> +arm_get_next_pcs_raw (struct arm_get_next_pcs *self, >> + CORE_ADDR pc) >> +{ >> + int byte_order = self->byte_order; >> + unsigned long pc_val; >> + unsigned long this_instr = 0; >> + unsigned long status; >> + CORE_ADDR nextpc; >> + struct regcache *regcache = self->regcache; >> + VEC (CORE_ADDR) *next_pcs = NULL; >> + >> + pc_val = (unsigned long) pc; >> + this_instr = self->ops->read_mem_uint (pc, 4, byte_order); > ^^^^^^^^^^ > >> - >> -/* Get the raw next address. PC is the current program counter, in >> - FRAME, which is assumed to be executing in ARM mode. >> - >> - The value returned has the execution state of the next instruction >> - encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is >> - in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory >> - address. */ >> - >> -static CORE_ADDR >> -arm_get_next_pc_raw (struct regcache *regcache, CORE_ADDR pc) >> -{ >> - struct gdbarch *gdbarch = get_regcache_arch (regcache); >> - enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); >> - enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); >> - unsigned long pc_val; >> - unsigned long this_instr; >> - unsigned long status; >> - CORE_ADDR nextpc; >> - >> - pc_val = (unsigned long) pc; >> - this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code); > ^^^^^^^^^^^^^^^^^^^ > > The code change above introduces a bug as I see. The original code uses > byte_order_for_code which is right to me, but it becomes byte_order > after the change. Patch below fixes it. > Thank you! Antoine