From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 91288 invoked by alias); 13 Oct 2015 17:31:58 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 91273 invoked by uid 89); 13 Oct 2015 17:31:57 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,SPF_HELO_PASS,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Tue, 13 Oct 2015 17:31:55 +0000 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (Postfix) with ESMTPS id B795A8E6EA; Tue, 13 Oct 2015 17:31:54 +0000 (UTC) Received: from [127.0.0.1] (ovpn01.gateway.prod.ext.ams2.redhat.com [10.39.146.11]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id t9DHVrQu012257; Tue, 13 Oct 2015 13:31:53 -0400 Message-ID: <561D4008.90009@redhat.com> Date: Tue, 13 Oct 2015 17:31:00 -0000 From: Pedro Alves User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Yao Qi CC: gdb-patches@sourceware.org Subject: Re: [PATCH] aarch64 multi-arch part 6: HW breakpoint on unaligned address References: <1444731060-16237-1-git-send-email-yao.qi@linaro.org> <561CE5D2.8030505@redhat.com> <861tcy6b84.fsf@gmail.com> In-Reply-To: <861tcy6b84.fsf@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-SW-Source: 2015-10/txt/msg00186.txt.bz2 On 10/13/2015 04:26 PM, Yao Qi wrote: > Pedro Alves writes: > >>> + { >>> + if (len == 3) >>> + len = 2; >> >> I think this warrants a comment. E.g., someone reading >> arm-linux-low.c:arm_linux_hw_point_initialize quite easily grasps >> what 3 means. >> > > How about the comment like this? > > if (len == 3) > { > /* LEN is 3 means the breakpoint is set on a 32-bit thumb > instruction. Set it to 2 to correctly encode length bit > mask in hardware/watchpoint control register. */ > len = 2; > } Sounds fine. > >>> diff --git a/gdb/nat/aarch64-linux-hw-point.c b/gdb/nat/aarch64-linux-hw-point.c >>> index bca6ec1..d15e518 100644 >>> --- a/gdb/nat/aarch64-linux-hw-point.c >>> +++ b/gdb/nat/aarch64-linux-hw-point.c >>> @@ -112,8 +112,17 @@ aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type, int len) >>> static int >>> aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len) >>> { >>> - unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT >>> - : AARCH64_HBP_ALIGNMENT; >>> + unsigned int alignment = 0; >>> + >>> + if (is_watchpoint) >>> + alignment = AARCH64_HWP_ALIGNMENT; >>> + else >>> + { >>> + /* Set alignment to 2 only if the current process is 32-bit, >>> + since thumb instruction can be 2-byte aligned. Otherwise, set >>> + alignment to AARCH64_HBP_ALIGNMENT. */ >>> + alignment = 2; >> >> Is some other code doing what the comment says? I'm not seeing >> any obvious 32-bit check. > > No, I don't do the 32-bit check here. Ideally, we should set alignment > to 2 only when the process is 32-bit, and still use 4 as alignment > otherwise. However, I don't find an easy way to do the 32-bit check > here, because this code is used by both GDB and GDBserver. We can do > the 32-bit check in GDB and GDBserver respectively, and pass the result > to nat/aarch64-linux-hw-point.c, but I don't like putting information down > multiple levels like this. At least the comment should be updated. It's quite misleading as is. Thanks, Pedro Alves