From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 116753 invoked by alias); 13 Oct 2015 11:07:02 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 116742 invoked by uid 89); 13 Oct 2015 11:07:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,SPF_HELO_PASS,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Tue, 13 Oct 2015 11:07:01 +0000 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (Postfix) with ESMTPS id E0F6A8C1D6; Tue, 13 Oct 2015 11:06:59 +0000 (UTC) Received: from [127.0.0.1] (ovpn01.gateway.prod.ext.ams2.redhat.com [10.39.146.11]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id t9DB6wPZ026142; Tue, 13 Oct 2015 07:06:59 -0400 Message-ID: <561CE5D2.8030505@redhat.com> Date: Tue, 13 Oct 2015 11:07:00 -0000 From: Pedro Alves User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Yao Qi , gdb-patches@sourceware.org Subject: Re: [PATCH] aarch64 multi-arch part 6: HW breakpoint on unaligned address References: <1444731060-16237-1-git-send-email-yao.qi@linaro.org> In-Reply-To: <1444731060-16237-1-git-send-email-yao.qi@linaro.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-SW-Source: 2015-10/txt/msg00172.txt.bz2 On 10/13/2015 11:11 AM, Yao Qi wrote: > --- a/gdb/gdbserver/linux-aarch64-low.c > +++ b/gdb/gdbserver/linux-aarch64-low.c > @@ -315,9 +315,12 @@ aarch64_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, > ret = -1; > } > else > - ret = > - aarch64_handle_breakpoint (targ_type, addr, len, 1 /* is_insert */, > - state); > + { > + if (len == 3) > + len = 2; I think this warrants a comment. E.g., someone reading arm-linux-low.c:arm_linux_hw_point_initialize quite easily grasps what 3 means. > + ret = aarch64_handle_breakpoint (targ_type, addr, len, > + 1 /* is_insert */, state); > + } > > if (show_debug_regs) > aarch64_show_debug_reg_state (state, "insert_point", addr, len, > @@ -353,9 +356,12 @@ aarch64_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, > aarch64_handle_watchpoint (targ_type, addr, len, 0 /* is_insert */, > state); > else > - ret = > - aarch64_handle_breakpoint (targ_type, addr, len, 0 /* is_insert */, > - state); > + { > + if (len == 3) > + len = 2; > + ret = aarch64_handle_breakpoint (targ_type, addr, len, > + 0 /* is_insert */, state); > + } > > if (show_debug_regs) > aarch64_show_debug_reg_state (state, "remove_point", addr, len, > diff --git a/gdb/nat/aarch64-linux-hw-point.c b/gdb/nat/aarch64-linux-hw-point.c > index bca6ec1..d15e518 100644 > --- a/gdb/nat/aarch64-linux-hw-point.c > +++ b/gdb/nat/aarch64-linux-hw-point.c > @@ -112,8 +112,17 @@ aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type, int len) > static int > aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len) > { > - unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT > - : AARCH64_HBP_ALIGNMENT; > + unsigned int alignment = 0; > + > + if (is_watchpoint) > + alignment = AARCH64_HWP_ALIGNMENT; > + else > + { > + /* Set alignment to 2 only if the current process is 32-bit, > + since thumb instruction can be 2-byte aligned. Otherwise, set > + alignment to AARCH64_HBP_ALIGNMENT. */ > + alignment = 2; Is some other code doing what the comment says? I'm not seeing any obvious 32-bit check. > + } > > if (addr & (alignment - 1)) > return 0; > @@ -445,7 +454,7 @@ aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr, > struct aarch64_debug_reg_state *state) > { > /* The hardware breakpoint on AArch64 should always be 4-byte > - aligned. */ > + aligned, but on AArch32, it can be 2-byte aligned. */ > if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len)) > return -1; > > -- 1.9.1 > Thanks, Pedro Alves