From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 95537 invoked by alias); 11 May 2015 11:31:33 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 95524 invoked by uid 89); 11 May 2015 11:31:33 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,SPF_HELO_PASS,SPF_PASS,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Mon, 11 May 2015 11:31:32 +0000 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) by mx1.redhat.com (Postfix) with ESMTPS id E08E68E76F; Mon, 11 May 2015 11:31:30 +0000 (UTC) Received: from [127.0.0.1] (ovpn01.gateway.prod.ext.ams2.redhat.com [10.39.146.11]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id t4BBVTK7026388; Mon, 11 May 2015 07:31:29 -0400 Message-ID: <55509310.6040909@redhat.com> Date: Mon, 11 May 2015 11:31:00 -0000 From: Pedro Alves User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 To: "Maciej W. Rozycki" CC: Yao Qi , gdb-patches@sourceware.org Subject: Re: [PATCH] [gdbserver] Disable conditional breakpoints on no-hardware-single-step targets References: <1430411029-12097-1-git-send-email-qiyaoltc@gmail.com> <554A368F.4060309@redhat.com> In-Reply-To: Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-SW-Source: 2015-05/txt/msg00248.txt.bz2 On 05/10/2015 02:04 AM, Maciej W. Rozycki wrote: > On Wed, 6 May 2015, Pedro Alves wrote: > >>> It is worse if the arm/thumb interworking is considered. Nowadays, >>> GDBserver arm backend unconditionally inserts arm breakpoint, >>> >>> /* Define an ARM-mode breakpoint; we only set breakpoints in the C >>> library, which is most likely to be ARM. If the kernel supports >>> clone events, we will never insert a breakpoint, so even a Thumb >>> C library will work; so will mixing EABI/non-EABI gdbserver and >>> application. */ >>> #ifndef __ARM_EABI__ >>> (const unsigned char *) &arm_breakpoint, >>> #else >>> (const unsigned char *) &arm_eabi_breakpoint, >>> #endif >>> >>> note that the comments are no longer valid as C library can be compiled >>> in thumb mode. >>> >>> When GDBserver steps over a breakpoint in arm mode function, which >>> returns to thumb mode, GDBserver will insert arm mode breakpoint by >>> mistake and the program will crash. GDBserver alone is unable to >>> determine the arm/thumb mode given a PC address. See how GDB does >>> it in arm-tdep.c:arm_pc_is_thumb. >> >> Of a random PC address no, but in gdbserver's case, I think that it >> would work, because we need it to step over a breakpoint that is >> at the current PC. So we could: >> >> #1 - Get the mode of the current PC from the thread's $cpsr register. >> >> #2 - Get the mode of the next PC by looking at the instruction that is >> about to be executed (at current PC). If bx and blx, which change >> modes, check the thumb bit of the destination address. >> For all other instructions, same mode as the current PC. > > A similar issue exists for the three MIPS ISA modes and gdbserver will > not have enough data to determine which of the two of the MIPS16 and > microMIPS instruction sets to use for the compressed mode. Only GDB knows > that, at the last resort having been told by the user. For breakpoints (z0/z1), GDB tells GDBserver the mode of instruction is encoded in the breakpoint's size. The tracepoint creation packets are older than that and only carry the address. They'll need to be extended to include the tracepoint's size as well. With that, when stepping past a gdb-set breakpoint/tracepoint, gdbserver can tell the mode of the instruction under the breakpoint/tracepoint from the breakpoint/tracepoint's size, as that's information that came from GDB. I assume that mode switches on MIPS are similar to ARM, with special branch instruction with mode encoded in in destination address? If so, starting from knowing the mode at PC, gdbserver should be able to determine the mode of all the potential next instructions on its own. Thanks, Pedro Alves