From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id Yh3iMLEv8mJenSMAWB0awg (envelope-from ) for ; Tue, 09 Aug 2022 05:58:09 -0400 Received: by simark.ca (Postfix, from userid 112) id B8E281E227; Tue, 9 Aug 2022 05:58:09 -0400 (EDT) Authentication-Results: simark.ca; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.a=rsa-sha256 header.s=default header.b=gDGalYOJ; dkim-atps=neutral X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-3.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,NICE_REPLY_A,RDNS_DYNAMIC, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 39CD11E13B for ; Tue, 9 Aug 2022 05:58:09 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8E9D33857C68 for ; Tue, 9 Aug 2022 09:58:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8E9D33857C68 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1660039087; bh=GdOWsAtFhqA3sD722V2/StvZo0BfNypdJaPBOHuFJLI=; h=Date:Subject:To:References:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=gDGalYOJQfn1TVq+Rkn+v65GPlhN6sgE61G18IcASATamcfQSaouLTtJLc9D1WUjZ e2mheBPMNPHpnaE/98ySA04c/xoD5sRTKEwKEY77M8CjUtdCDz1cILOZXTdMPqJ9lU I2vke88rt3PW2dK7vMdnMhRW13jZGwaXm5uUdzwM= Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.220.29]) by sourceware.org (Postfix) with ESMTPS id C25BD3858004 for ; Tue, 9 Aug 2022 09:57:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C25BD3858004 Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id EF6D51FACB; Tue, 9 Aug 2022 09:57:46 +0000 (UTC) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id D5D8813AA1; Tue, 9 Aug 2022 09:57:46 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id tx8eM5ov8mLNRAAAMHmgww (envelope-from ); Tue, 09 Aug 2022 09:57:46 +0000 Message-ID: <54574882-62aa-ee50-f878-7aaff48d9efb@suse.de> Date: Tue, 9 Aug 2022 11:57:46 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH] [Arm] Fix endianness handling for arm record self tests Content-Language: en-US To: Luis Machado , gdb-patches@sourceware.org References: <20220808101203.168954-1-luis.machado@arm.com> <6fe1ae85-a72a-e256-1c88-f9a9b303c0b8@suse.de> In-Reply-To: <6fe1ae85-a72a-e256-1c88-f9a9b303c0b8@suse.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Tom de Vries via Gdb-patches Reply-To: Tom de Vries Cc: mark@klomp.org Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" On 8/9/22 11:43, Tom de Vries wrote: > On 8/8/22 12:12, Luis Machado wrote: >> The arm record tests handle 16-bit and 32-bit thumb instructions, but the >> code is laid out in a way that handles the 32-bit thumb instructions as >> two 16-bit parts. >> >> This is fine, but it is prone to host-endianness issues given how the two >> 16-bit parts are stored and how they are accessed later on. Arm is >> little-endian by default, so running this test with a GDB built with >> --enable-targets=all and on a big endian host will run into the >> following: >> >> Running selftest arm-record. >> Process record and replay target doesn't support syscall number -2036195 >> Process record does not support instruction 0x7f70ee1d at address 0x0. >> Self test failed: self-test failed at >> ../../binutils-gdb/gdb/arm-tdep.c:14482 >> >> Investigating this a bit further, there seems to be a chance to do a >> simple >> fix through a type template, using uint16_t for 16-bit thumb instructions >> and uint32_t for 32-bit thumb instructions. >> >> This patch implements this. >> > > Hi Luis, > > LGTM. > > I noticed btw that this: > ... > diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c > index 57b865a0819..1e6d9ba65be 100644 > --- a/gdb/arm-tdep.c > +++ b/gdb/arm-tdep.c > @@ -14489,6 +14489,29 @@ arm_record_test (void) >      SELF_CHECK (arm_record.reg_rec_count == 1); >      SELF_CHECK (arm_record.arm_regs[0] == 7); >    } > + > + > +  /* 32-bit instructions.  */ > +  { > +    arm_insn_decode_record arm_record; > + > +    memset (&arm_record, 0, sizeof (arm_insn_decode_record)); > +    arm_record.gdbarch = gdbarch; > + > +    /* Use the endian-free representation of the instruction here.  The > test > +       will handle endianness conversions.  */ > +    static const uint32_t insns[] = { > +      /* mov     r5, r0 */ > +      0xe1a05000, > +    }; > + > +    enum bfd_endian endian = gdbarch_byte_order_for_code > (arm_record.gdbarch); > +    instruction_reader_thumb reader (endian, insns); > +    int ret = decode_insn (reader, &arm_record, ARM_RECORD, > +                          ARM_INSN_SIZE_BYTES); > + > +    SELF_CHECK (ret == 0); > +  } >  } > >  /* Instruction reader from manually cooked instruction sequences.  */ > ... > works fine, so I wonder if instruction_reader_thumb is a misnomer, > perhaps we call it instruction_reader_selftest or some such, and add the > arm32 insn to cover that case? > > Also I wondered if these checks > ... >     SELF_CHECK (len == 4 || len == 2); >     SELF_CHECK (memaddr % 2 == 0); >     SELF_CHECK ((memaddr / 2) < m_insns_size); > ... > can be made more specific based on the template argument T. Also, I think this is more clear: ... -store_unsigned_integer (buf, sizeof (T), m_endian, m_insns[memaddr / 2]); +store_unsigned_integer (buf, sizeof (T), m_endian, m_insns[memaddr / sizeof (T)]); ... Thanks, - Tom