From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12044 invoked by alias); 12 Aug 2014 09:43:39 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 12028 invoked by uid 89); 12 Aug 2014 09:43:38 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.0 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 12 Aug 2014 09:43:35 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Tue, 12 Aug 2014 10:43:32 +0100 Received: from [10.1.208.33] ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 12 Aug 2014 10:43:30 +0100 Message-ID: <53E9E1C2.6010707@arm.com> Date: Tue, 12 Aug 2014 09:43:00 -0000 From: Richard Earnshaw User-Agent: Mozilla/5.0 (X11; Linux i686 on x86_64; rv:15.0) Gecko/20120907 Thunderbird/15.0.1 MIME-Version: 1.0 To: Catalin Udma CC: "gdb-patches@sourceware.org" Subject: Re: [PATCH] aarch64/gdbserver: fix floating point registers display References: <1407835166-827-1-git-send-email-catalin.udma@freescale.com> In-Reply-To: <1407835166-827-1-git-send-email-catalin.udma@freescale.com> X-MC-Unique: 114081210433211701 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2014-08/txt/msg00194.txt.bz2 On 12/08/14 10:19, Catalin Udma wrote: > When using aarch64 gdb with gdbserver, floating point registers are > not correctly displayed, as below: > (gdb) info registers fpsr fpcr > fpsr > fpcr > Also, the offset for floating point v0-v31 registers in gdbserver > is wrong because it is computed based on 32-bit size of CPSR register > as defined in the regformat/aarch64.dat file >=20 > To fix these problems, the missing fpsr and fpcr registers are added > when floating point registers are read/write and the aarch64.dat file > is updated to use the correct CPSR size of 64-bits accordingly to the > definition in aarch64-core.xml This doesn't seem right to me. The CPSR is a 32-bit register, not a 64-bit one. R. >=20 > gdb/ > 2014-08-12 Catalin Udma >=20 > * regformats/aarch64.dat (cpsr): Change to be 64bit. >=20 > gdb/gdbserver/ > 2014-08-12 Catalin Udma >=20 > * linux-aarch64-low.c (AARCH64_FPSR_REGNO): New define. > (AARCH64_FPCR_REGNO): Likewise. > (AARCH64_NUM_REGS): Update to include fpsr/fpcr registers. > (aarch64_fill_fpregset): Add missing fpsp/fpcr registers. > (aarch64_store_fpregset): Likewise. > --- > gdb/gdbserver/linux-aarch64-low.c | 8 +++++++- > gdb/regformats/aarch64.dat | 2 +- > 2 files changed, 8 insertions(+), 2 deletions(-) >=20 > diff --git a/gdb/gdbserver/linux-aarch64-low.c b/gdb/gdbserver/linux-aarc= h64-low.c > index 6066e15..3453b2e 100644 > --- a/gdb/gdbserver/linux-aarch64-low.c > +++ b/gdb/gdbserver/linux-aarch64-low.c > @@ -46,8 +46,10 @@ extern const struct target_desc *tdesc_aarch64; > #define AARCH64_PC_REGNO 32 > #define AARCH64_CPSR_REGNO 33 > #define AARCH64_V0_REGNO 34 > +#define AARCH64_FPSR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM) > +#define AARCH64_FPCR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 1) >=20=20 > -#define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM) > +#define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 2) >=20=20 > static int > aarch64_regmap [] =3D > @@ -255,6 +257,8 @@ aarch64_fill_fpregset (struct regcache *regcache, voi= d *buf) >=20=20 > for (i =3D 0; i < AARCH64_V_REGS_NUM; i++) > collect_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]); > + collect_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr); > + collect_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr); > } >=20=20 > static void > @@ -265,6 +269,8 @@ aarch64_store_fpregset (struct regcache *regcache, co= nst void *buf) >=20=20 > for (i =3D 0; i < AARCH64_V_REGS_NUM; i++) > supply_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]); > + supply_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr); > + supply_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr); > } >=20=20 > /* Debugging of hardware breakpoint/watchpoint support. */ > diff --git a/gdb/regformats/aarch64.dat b/gdb/regformats/aarch64.dat > index afe1028..0d32183 100644 > --- a/gdb/regformats/aarch64.dat > +++ b/gdb/regformats/aarch64.dat > @@ -35,7 +35,7 @@ expedite:x29,sp,pc > 64:x30 > 64:sp > 64:pc > -32:cpsr > +64:cpsr > 128:v0 > 128:v1 > 128:v2 >=20