From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25341 invoked by alias); 24 Apr 2014 11:49:05 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 25327 invoked by uid 89); 24 Apr 2014 11:49:05 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 24 Apr 2014 11:49:03 +0000 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id s3OBmxSs010151 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 24 Apr 2014 07:48:59 -0400 Received: from [127.0.0.1] (ovpn01.gateway.prod.ext.ams2.redhat.com [10.39.146.11]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id s3OBmvhJ016369; Thu, 24 Apr 2014 07:48:58 -0400 Message-ID: <5358FA29.4010607@redhat.com> Date: Thu, 24 Apr 2014 11:49:00 -0000 From: Pedro Alves User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130625 Thunderbird/17.0.7 MIME-Version: 1.0 To: Michael Sturm CC: palves@redhat.com, eliz@gnu.org, mark.kettenis@xs4all.nl, walfred.tedeschi@intel.com, gdb-patches@sourceware.org Subject: Re: [PATCH V5 0/3] Intel(R) AVX-512 register support References: <1398258160-9070-1-git-send-email-michael.sturm@intel.com> In-Reply-To: <1398258160-9070-1-git-send-email-michael.sturm@intel.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-SW-Source: 2014-04/txt/msg00493.txt.bz2 On 04/23/2014 02:02 PM, Michael Sturm wrote: > Pedro, > > thanks for your review. We've addressed the comments you made regarding the > test case and the manual content. We do agree to your comment > regarding sharing code between GDB and GDBserver. We would prefer to > make this change in a patch dedicated to unify XSAVE buffer access > between GDB and GDBserver. > Would you agree to that and approve committing this series? Definitely. I wasn't suggesting making that as part of this patch. Oh, > This patch series adds support for the Intel(R) Advanced Vector Extensions 512 > (Intel(R) AVX-512) registers. Native and remote debugging are covered by this > patch series. > > Intel(R) AVX-512 is an extension to AVX to support 512-bit wide SIMD registers > in 64-bit mode (XMM0-XMM31, YMM0-YMM31, ZMM0-ZMM31). The number of available > registers in 32-bit mode is still 8 (XMM0-7, YMM0-7, ZMM0-7). The lower > 256-bits of the ZMM registers are aliased to the respective 256-bit YMM > registers. The lower 128-bits are aliased to the respective 128-bit XMM > registers. > > There are also 8 new, dedicated mask registers (K0-K7) in both 32-bit mode > and 64-bit mode. > > For more information please see > Intel(R) Developer Zone: Intel(R) AVX > http://software.intel.com/en-us/intel-isa-extensions#pid-16007-1495 > > Intel(R) Architecture Instruction Set Extensions Programming Reference: > http://software.intel.com/en-us/file/319433-017pdf I notice that this info is only in the series cover letter, which never makes it to the commit log. Would you mind putting it in at least the commit log entry of the GDB patch (tweaked a little to not say "series")? (pre-approved, no need for another round of review for that). Thanks, -- Pedro Alves