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b=QgnfeI5n7ZTsd5TEfWBFj0kzB4PYguoDE2J9JQkpdGquARX87I+4s6WPH0ZUZPEUa 9Cn8hQRLmrr998dZTMV1QJTuY5SuuIBHF8plTYxWJgi4iM2gB2002vbxQD0vnlOrq7 xiAxQofSd+rZ+aRIAeWp0AZg9SY44ry1M3EAHQ/sS1PeQT6vo35hchFDXkF2xUFTkn owJy3yTSFLZNhsJ/ynuVRc23cUdenIKuVFGZzbiMvfKZ6ZXgv2clnPOYQzX4ZtPm9a Ytq8XT5iGp+2k0ni6hUHp9qKv2QPOzjsBz/ZHIF7pb8DEgNN/gkQ4QJcP75LbEslfY tInpWN+W2plFA== X-Virus-Scanned: amavis at zimbra.eb.localhost Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavis, port 10026) with ESMTP id NBEzi7pG6x7Q; Tue, 18 Aug 2026 13:45:10 +0200 (CEST) Received: from zimbra.eb.localhost (zimbra.eb.localhost [192.168.96.204]) by mail.embedded-brains.de (Postfix) with ESMTP id EA52A480151; Tue, 18 Aug 2026 13:45:10 +0200 (CEST) Date: Tue, 18 Aug 2026 13:45:10 +0200 (CEST) From: Sebastian Huber To: Andrew Burgess Cc: gdb-patches Message-ID: <533358179.11798.1787053510438.JavaMail.zimbra@embedded-brains.de> In-Reply-To: <87qzjv1zh3.fsf@redhat.com> References: <20260816234357.278358-1-sebastian.huber@embedded-brains.de> <20260816234357.278358-5-sebastian.huber@embedded-brains.de> <87qzjv1zh3.fsf@redhat.com> Subject: Re: [PATCH 4/4] sim/mips: Recognise a software interrupt request MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [192.168.96.204] X-Mailer: Zimbra 10.1.20_GA_4893 (ZimbraWebClient - FF140 (Linux)/10.1.20_GA_4894) Thread-Topic: sim/mips: Recognise a software interrupt request Thread-Index: +uusT+21xaJw5eEKeYiCjpo0KWDbxA== X-DKIM-Status: pass [(embedded-brains.de) - 78.47.166.52] X-Virus-Scanned: Clear (ClamAV 1.4.3/28096/Tue Aug 18 08:27:40 2026) X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org ----- Am 18. Aug 2026 um 12:42 schrieb Andrew Burgess aburgess@redhat.com: > Sebastian Huber writes: >=20 >> Add support for the Cause.IP0 and Cause.IP1 software generated >> interrupts defined by the MIPS Architecture For Programmers Volume III: >> The MIPS Privileged Resource Architecture. >> >> Deliver it from the event queue rather than in place, because >> signal_exception() leaves the handler address in the program counter for >> an interrupt and the instruction being executed would overwrite it. >> >> Signed-off-by: Sebastian Huber >> --- >> sim/mips/interp.c | 64 +++++++++++++++++++++++++++++++++++++++++++-- >> sim/mips/sim-main.h | 2 ++ >> 2 files changed, 64 insertions(+), 2 deletions(-) >> >> diff --git a/sim/mips/interp.c b/sim/mips/interp.c >> index 5dbd1482b99..fddb96d00ed 100644 >> --- a/sim/mips/interp.c >> +++ b/sim/mips/interp.c >> @@ -295,6 +295,58 @@ static const OPTION mips_options[] =3D >> =20 >> int interrupt_pending; >> =20 >> +/* An interrupt is requested while the interrupts are enabled and a pen= ding >> + bit of the Cause register meets its mask bit in the Status register: >> + >> + Status.IE =3D 1, Status.EXL =3D 0, Status.ERL =3D 0, Cause.IP & St= atus.IM !=3D 0 >> + >> + MIPS Architecture For Programmers Volume III: The MIPS Privileged Re= source >> + Architecture, the Interrupts chapter. The R3000 generation, which t= he >> + R3900 belongs to, has no exception level and disables the interrupts= by >> + shifting the interrupt enable stack of its Status register instead, = so only >> + the current enable takes part; see the IDT R30xx Family Software Ref= erence >> + Manual, the Status register of the CPU control chapter. */ >> +static int >> +interrupt_requested (sim_cpu *cpu) >> +{ >> + if ((SR & status_IE) =3D=3D 0) >> + return 0; >> + >> +#ifndef SUBTARGET_R3900 >> + if ((SR & (status_EXL | status_ERL)) !=3D 0) >> + return 0; >> +#endif >> + >> + /* Only the software interrupts. A hardware interrupt keeps its pend= ing bit >> + set until its device is served. The device model delivers it. */ >=20 > Two spaces after 'served.' please. >=20 >> + return ((CAUSE >> cause_IPSW_shift) & (SR >> status_IM_shift) >> +=09 & cause_IPSW_mask) !=3D 0; >> +} >> + >> +static void >> +software_interrupt_event (SIM_DESC sd, void *data) >> +{ >> + sim_cpu *cpu =3D STATE_CPU (sd, 0); >> + address_word cia =3D CPU_PC_GET (cpu); >> + >> + /* Recheck, because the write which scheduled this may have been undo= ne in >> + the meantime. */ >> + if (interrupt_requested (cpu)) >> + SignalExceptionInterrupt (0); >> +} >> + >> +/* Deliver a pending interrupt at the next instruction boundary. It ca= nnot be >> + delivered here: signal_exception() leaves the handler address in the= program >> + counter for an interrupt and the instruction which is being executed= would >> + overwrite it. This is why the hardware interrupts arrive through th= e event >> + queue as well. */ >> +static void >> +check_interrupts (SIM_DESC sd, sim_cpu *cpu) >> +{ >> + if (interrupt_requested (cpu)) >> + sim_events_schedule (sd, 1, software_interrupt_event, NULL); >> +} >> + >> void >> interrupt_event (SIM_DESC sd, void *data) >> { >> @@ -2269,14 +2321,20 @@ decode_coproc (SIM_DESC sd, >> =09=09if (op =3D=3D cp0_mfc0 || op =3D=3D cp0_dmfc0) >> =09=09 GPR[rt] =3D SR; >> =09=09else >> -=09=09 SR =3D GPR[rt]; >> +=09=09 { >> +=09=09 SR =3D GPR[rt]; >> +=09=09 check_interrupts (sd, cpu); >> +=09=09 } >> =09=09break; >> =09=09/* 13 =3D Cause R4000 VR4100 VR4300 */ >> =09 case 13: >> =09=09if (op =3D=3D cp0_mfc0 || op =3D=3D cp0_dmfc0) >> =09=09 GPR[rt] =3D CAUSE; >> =09=09else >> -=09=09 CAUSE =3D GPR[rt]; >> +=09=09 { >> +=09=09 CAUSE =3D GPR[rt]; >> +=09=09 check_interrupts (sd, cpu); >> +=09=09 } >> =09=09break; >> =09=09/* 14 =3D EPC R4000 VR4100 VR4300 */ >> =09 case 14: >> @@ -2391,6 +2449,7 @@ decode_coproc (SIM_DESC sd, >> =09 { >> =09=09PC =3D EPC; >> =09=09SR &=3D ~status_EXL; >> +=09=09check_interrupts (sd, cpu); >> =09 } >=20 > This is the ERET case for handling the situation where the ERL bit is > cleared. If I reproduce your patched code, but with more context, we > see this: >=20 > /* ERET */ > if (SR & status_ERL) > { > /* Oops, not yet available */ > sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet"); > PC =3D EPC; > SR &=3D ~status_ERL; > } > else > { > PC =3D EPC; > SR &=3D ~status_EXL; > check_interrupts (sd, cpu); > } >=20 > Now clearly the `if` block is broken, we're setting PC from the wrong > place I think. But if this block _was_ ever fixed then we're going to > need a check_interrupts call on that path too, right? >=20 > My suggestion is that we move the check_interrupts call after the `else` > block, like this: >=20 > /* ERET */ > if (SR & status_ERL) > { > /* Oops, not yet available */ > sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet"); > PC =3D EPC; > SR &=3D ~status_ERL; > } > else > { > PC =3D EPC; > SR &=3D ~status_EXL; > } > check_interrupts (sd, cpu); >=20 > This doesn't fix the `if` block, but if someone ever does fix that path, > then the check_interrupts call will be in place ready for them. >=20 > What do you think? Thanks for your review. I used the RTEMS test suite as my main driver for t= he changes. Yes, I think that moving the check after the `if` block makes sense. >=20 > If you're happy to accept the two changes then: >=20 > Approved-By: Andrew Burgess I am only an occasional contributor, so I am not sure if I understood it co= rrectly. 1. I remove the Signed-off-by from all four patches. 2. I fix all your review comments. 3. I run my tests again. 4. I add the Approved-By: Andrew Burgess to all four = commits. 5. I don't send a v2 version to the patches list. 6. I check in the updated patch set directly. Kind regards, Sebastian --=20 embedded brains GmbH & Co. KG Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.huber@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht M=C3=BCnchen Registernummer: HRB 157899 Vertretungsberechtigte Gesch=C3=A4ftsf=C3=BChrer: Peter Rasmussen, Thomas D= =C3=B6rfler Unsere Datenschutzerkl=C3=A4rung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/