Re: [PATCH 1/2] GDB process record and reverse debugging improvements for arm*-linux*

[Yao Qi <yao@codesourcery.com>]

Patch looks good to me, and you still need a maintainer's approval.

Some of the comments are too long.  Please make sure they don't exceed 
the limitation (around 74 characters should be fine).

On 11/08/2013 11:19 AM, Omair Javaid wrote:
> +/* Handler for thumb2 ld/st dual, ld/st exclusive, table branch
> instructions.  */
> +

here.

> +static int
> +thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r)
> +{
> +  struct regcache *reg_cache = thumb2_insn_r->regcache;
> +

....

> +
> +/* Decodes thumb2 instruction type and return an instruction id.  */
> +
> +static unsigned int
> +thumb2_record_decode_inst_id (uint32_t thumb2_insn)
> +{
> +  uint32_t op = 0;
> +  uint32_t op1 = 0;
> +  uint32_t op2 = 0;
> +
> +  op = bit (thumb2_insn, 15);
> +  op1 = bits (thumb2_insn, 27, 28);
> +  op2 = bits (thumb2_insn, 20, 26);
> +
> +  if (op1 == 0x01)
> +    {
> +      if (!(op2 & 0x64 ))
> +        {
> +          /* Load/store multiple instruction.  */
> +          return 0;
> +        }
> +      else if (!((op2 & 0x64) ^ 0x04))
> +        {
> +          /* Load/store dual, load/store exclusive, table branch
> instruction.  */

and here.


> +          return 1;
> +        }
> +      else if (!((op2 & 0x20) ^ 0x20))
> +        {
> +          /* Data-processing (shifted register).  */
> +          return 2;
> +        }
> +      else if (op2 & 0x40)
> +        {
> +          /* Co-processor instructions.  */
> +          return 3;
> +        }
> +    }
> +  else if (op1 == 0x02)
> +    {
> +      if (op)
> +        {
> +          /* Branches and miscellaneous control instructions.  */
> +          return 6;
> +        }
> +      else if (op2 & 0x20)
> +        {
> +          /* Data-processing (plain binary immediate) instruction.  */
> +          return 5;
> +        }
> +      else
> +        {
> +          /* Data-processing (modified immediate).  */
> +          return 4;
> +        }
> +    }
> +  else if (op1 == 0x03)
> +   {
> +      if (!(op2 & 0x71 ))
> +        {
> +          /* Store single data item.  */
> +          return 7;
> +        }
> +      else if (!((op2 & 0x71) ^ 0x10))
> +        {
> +          /* Advanced SIMD element or structure load/store
> instructions.  */

here.

> +          return 8;
> +        }
> +      else if (!((op2 & 0x67) ^ 0x01))
> +        {
> +          /* Load byte, memory hints instruction.  */
> +          return 9;
> +        }
> +      else if (!((op2 & 0x67) ^ 0x03))
> +        {
> +          /* Load halfword, memory hints instruction.  */
> +          return 10;
> +        }
> +      else if (!((op2 & 0x67) ^ 0x05))
> +        {
> +          /* Load word instruction.  */
> +          return 11;
> +        }
> +      else if (!((op2 & 0x70) ^ 0x20))
> +        {
> +          /* Data-processing (register) instruction.  */
> +          return 12;
> +        }
> +      else if (!((op2 & 0x78) ^ 0x30))
> +        {
> +          /* Multiply, multiply accumulate, absolute difference
> instruction.  */

here.

> +          return 13;
> +        }
> +      else if (!((op2 & 0x78) ^ 0x38))
> +        {
> +          /* Long multiply, long multiply accumulate, and divide.  */
> +          return 14;
> +        }
> +      else if (op2 & 0x40)
> +        {
> +          /* Co-processor instructions.  */
> +          return 15;
> +        }
> +   }
> +
> +  return -1;
> +}
>
>   /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0
> on success
>   and positive val on fauilure.  */
> @@ -12452,7 +13034,7 @@ decode_insn (insn_decode_record *arm_rec
>       arm_record_ld_st_reg_offset,        /* 011.  */
>       arm_record_ld_st_multiple,          /* 100.  */
>       arm_record_b_bl,                    /* 101.  */
> -    arm_record_coproc,                  /* 110.  */
> +    arm_record_unsupported_insn,                  /* 110.  */
>       arm_record_coproc_data_proc         /* 111.  */
>     };
>
> @@ -12469,6 +13051,27 @@ decode_insn (insn_decode_record *arm_rec
>       thumb_record_branch                /* 111.  */
>     };
>
> +  /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
> instruction.  */

here.

-- 
Yao (齐尧)