From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16907 invoked by alias); 13 Jun 2016 14:12:14 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 16887 invoked by uid 89); 13 Jun 2016 14:12:13 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.3 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD,SPF_HELO_PASS autolearn=ham version=3.3.2 spammy=Lin, halves, sixteen X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Mon, 13 Jun 2016 14:12:12 +0000 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 4B674C049E1D; Mon, 13 Jun 2016 14:12:11 +0000 (UTC) Received: from [127.0.0.1] (ovpn01.gateway.prod.ext.ams2.redhat.com [10.39.146.11]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u5DEC9Qr017536; Mon, 13 Jun 2016 10:12:10 -0400 Subject: Re: [PATCH v2] AndesTech NDS32 port To: Yan-Ting Lin , Yao Qi References: <3561f390-ea41-2ee3-a5a9-d870429497c3@gmail.com> <868typxi5r.fsf@gmail.com> Cc: gdb-patches@sourceware.org From: Pedro Alves Message-ID: <52349f93-90e6-eca9-c368-6de28a490509@redhat.com> Date: Mon, 13 Jun 2016 14:12:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-SW-Source: 2016-06/txt/msg00227.txt.bz2 On 06/06/2016 04:13 PM, Yan-Ting Lin wrote: > +@emph{Note:} The first sixteen 64-bit double-precision floating-point > +registers are overlapped with the thirty-two 32-bit single-precision > +floating-point registers. The 32-bit single-precision registers, if > +not being listed explicitly, will be synthesized from halves of the > +overlapping 64-bit double-precision registers. Listing 32-bit > +single-precision registers explicitly is deprecated, and the > +support to it could be totally removed some day. Why do we need to support explicitly-listed 32-bit single-precision registers at all? The patch looks good to me otherwise, too. Thanks, Pedro Alves