[PATCH 04/22] [GDBserver] Multi-process + multi-arch: GNU/Linux PowerPC

Pedro Alves
2013-05-29T16:25:48Z

This adjusts the GNU/Linux PowerPC port to new interfaces.

Previously tested on PowerPC GDBserver Fedora 16, no regressions.

2013-05-29 Pedro Alves <palves@redhat.com>

* linux-ppc-low.c (tdesc_powerpc_32l, tdesc_powerpc_altivec32l)
(tdesc_powerpc_cell32l, tdesc_powerpc_vsx32l)
(tdesc_powerpc_isa205_32l, tdesc_powerpc_isa205_altivec32l)
(tdesc_powerpc_isa205_vsx32l, tdesc_powerpc_e500l)
(tdesc_powerpc_64l, tdesc_powerpc_altivec64l)
(tdesc_powerpc_cell64l, tdesc_powerpc_vsx64l)
(tdesc_powerpc_isa205_64l, tdesc_powerpc_isa205_altivec64l)
(tdesc_powerpc_isa205_vsx64l): Declare.
(ppc_cannot_store_register, ppc_collect_ptrace_register)
(ppc_supply_ptrace_register, parse_spufs_run, ppc_get_pc)
(ppc_set_pc, ppc_get_hwcap): Adjust.
(ppc_usrregs_info): Forward declare.
(!__powerpc64__) ppc_regmap_adjusted: New global.
(ppc_arch_setup): Adjust to the current process'es target
description.
(ppc_fill_vsxregset, ppc_store_vsxregset, ppc_fill_vrregset)
(ppc_store_vrregset, ppc_fill_evrregset, ppc_store_evrregse)
(ppc_store_evrregset): Adjust.
(target_regsets): Rename to ...
(ppc_regsets): ... this, and make static.
(ppc_usrregs_info, ppc_regsets_info, regs_info): New globals.
(ppc_regs_info): New function.
(the_low_target): Adjust.
(initialize_low_arch): New function.
---
gdb/gdbserver/linux-ppc-low.c | 168 +++++++++++++++++++++++++++++++----------
1 file changed, 126 insertions(+), 42 deletions(-)

diff --git a/gdb/gdbserver/linux-ppc-low.c b/gdb/gdbserver/linux-ppc-low.c
index 1c81c79..4ac032c 100644
--- a/gdb/gdbserver/linux-ppc-low.c
+++ b/gdb/gdbserver/linux-ppc-low.c
@@ -64,6 +64,22 @@ void init_registers_powerpc_isa205_altivec64l (void);
/* Defined in auto-generated file powerpc-isa205-vsx64l.c. */
void init_registers_powerpc_isa205_vsx64l (void);

+extern struct target_desc *tdesc_powerpc_32l;
+extern struct target_desc *tdesc_powerpc_altivec32l;
+extern struct target_desc *tdesc_powerpc_cell32l;
+extern struct target_desc *tdesc_powerpc_vsx32l;
+extern struct target_desc *tdesc_powerpc_isa205_32l;
+extern struct target_desc *tdesc_powerpc_isa205_altivec32l;
+extern struct target_desc *tdesc_powerpc_isa205_vsx32l;
+extern struct target_desc *tdesc_powerpc_e500l;
+extern struct target_desc *tdesc_powerpc_64l;
+extern struct target_desc *tdesc_powerpc_altivec64l;
+extern struct target_desc *tdesc_powerpc_cell64l;
+extern struct target_desc *tdesc_powerpc_vsx64l;
+extern struct target_desc *tdesc_powerpc_isa205_64l;
+extern struct target_desc *tdesc_powerpc_isa205_altivec64l;
+extern struct target_desc *tdesc_powerpc_isa205_vsx64l;
+
#define ppc_num_regs 73

/* This sometimes isn't defined. */
@@ -147,15 +163,18 @@ static int ppc_regmap_e500[] =
static int
ppc_cannot_store_register (int regno)
{
+ struct target_desc *tdesc = current_process ()->tdesc;
+
#ifndef __powerpc64__
/* Some kernels do not allow us to store fpscr. */
- if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE) && regno == find_regno ("fpscr"))
+ if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)
+ && regno == find_regno (tdesc, "fpscr"))
return 2;
#endif

/* Some kernels do not allow us to store orig_r3 or trap. */
- if (regno == find_regno ("orig_r3")
- || regno == find_regno ("trap"))
+ if (regno == find_regno (tdesc, "orig_r3")
+ || regno == find_regno (tdesc, "trap"))
return 2;

return 0;
@@ -170,7 +189,7 @@ ppc_cannot_fetch_register (int regno)
static void
ppc_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
{
- int size = register_size (regno);
+ int size = register_size (regcache->tdesc, regno);

memset (buf, 0, sizeof (long));

@@ -184,7 +203,7 @@ static void
ppc_supply_ptrace_register (struct regcache *regcache,
int regno, const char *buf)
{
- int size = register_size (regno);
+ int size = register_size (regcache->tdesc, regno);
if (size < sizeof (long))
supply_register (regcache, regno, buf + sizeof (long) - size);
else
@@ -205,7 +224,7 @@ parse_spufs_run (struct regcache *regcache, int *fd, CORE_ADDR *addr)
int curr_insn;
int curr_r0;

- if (register_size (0) == 4)
+ if (register_size (regcache->tdesc, 0) == 4)
{
unsigned int pc, r0, r3, r4;
collect_register_by_name (regcache, "pc", &pc);
@@ -257,7 +276,7 @@ ppc_get_pc (struct regcache *regcache)
return ((CORE_ADDR)1 << 63)
| ((CORE_ADDR)fd << 32) | (CORE_ADDR) (pc - 4);
}
- else if (register_size (0) == 4)
+ else if (register_size (regcache->tdesc, 0) == 4)
{
unsigned int pc;
collect_register_by_name (regcache, "pc", &pc);
@@ -282,7 +301,7 @@ ppc_set_pc (struct regcache *regcache, CORE_ADDR pc)
unsigned int newpc = pc;
(*the_target->write_memory) (addr, (unsigned char *) &newpc, 4);
}
- else if (register_size (0) == 4)
+ else if (register_size (regcache->tdesc, 0) == 4)
{
unsigned int newpc = pc;
supply_register_by_name (regcache, "pc", &newpc);
@@ -298,7 +317,8 @@ ppc_set_pc (struct regcache *regcache, CORE_ADDR pc)
static int
ppc_get_hwcap (unsigned long *valp)
{
- int wordsize = register_size (0);
+ struct target_desc *tdesc = current_process ()->tdesc;
+ int wordsize = register_size (tdesc, 0);
unsigned char *data = alloca (2 * wordsize);
int offset = 0;

@@ -330,9 +350,16 @@ ppc_get_hwcap (unsigned long *valp)
return 0;
}

+/* Forward declaration. */
+static struct usrregs_info ppc_usrregs_info;
+#ifndef __powerpc64__
+static int ppc_regmap_adjusted;
+#endif
+
static void
ppc_arch_setup (void)
{
+ struct target_desc *tdesc;
#ifdef __powerpc64__
long msr;
struct regcache *regcache;
@@ -340,20 +367,21 @@ ppc_arch_setup (void)
/* On a 64-bit host, assume 64-bit inferior process with no
AltiVec registers. Reset ppc_hwcap to ensure that the
collect_register call below does not fail. */
- init_registers_powerpc_64l ();
+ tdesc = tdesc_powerpc_64l;
+ current_process ()->tdesc = tdesc;
ppc_hwcap = 0;

/* Only if the high bit of the MSR is set, we actually have
a 64-bit inferior. */
- regcache = new_register_cache ();
- fetch_inferior_registers (regcache, find_regno ("msr"));
+ regcache = new_register_cache (tdesc);
+ fetch_inferior_registers (regcache, find_regno (tdesc, "msr"));
collect_register_by_name (regcache, "msr", &msr);
free_register_cache (regcache);
if (msr < 0)
{
ppc_get_hwcap (&ppc_hwcap);
if (ppc_hwcap & PPC_FEATURE_CELL)
- init_registers_powerpc_cell64l ();
+ tdesc = tdesc_powerpc_cell64l;
else if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
{
/* Power ISA 2.05 (implemented by Power 6 and newer processors)
@@ -364,59 +392,67 @@ ppc_arch_setup (void)
Point, we check if that feature is available to decide the size
of the FPSCR. */
if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
- init_registers_powerpc_isa205_vsx64l ();
+ tdesc = tdesc_powerpc_isa205_vsx64l;
else
- init_registers_powerpc_vsx64l ();
+ tdesc = tdesc_powerpc_vsx64l;
}
else if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
{
if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
- init_registers_powerpc_isa205_altivec64l ();
+ tdesc = tdesc_powerpc_isa205_altivec64l;
else
- init_registers_powerpc_altivec64l ();
+ tdesc = tdesc_powerpc_altivec64l;
}

+ current_process ()->tdesc = tdesc;
return;
}
#endif

/* OK, we have a 32-bit inferior. */
- init_registers_powerpc_32l ();
+ tdesc = tdesc_powerpc_32l;
+ current_process ()->tdesc = tdesc;

ppc_get_hwcap (&ppc_hwcap);
if (ppc_hwcap & PPC_FEATURE_CELL)
- init_registers_powerpc_cell32l ();
+ tdesc = tdesc_powerpc_cell32l;
else if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
{
if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
- init_registers_powerpc_isa205_vsx32l ();
+ tdesc = tdesc_powerpc_isa205_vsx32l;
else
- init_registers_powerpc_vsx32l ();
+ tdesc = tdesc_powerpc_vsx32l;
}
else if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
{
if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
- init_registers_powerpc_isa205_altivec32l ();
+ tdesc = tdesc_powerpc_isa205_altivec32l;
else
- init_registers_powerpc_altivec32l ();
+ tdesc = tdesc_powerpc_altivec32l;
}

/* On 32-bit machines, check for SPE registers.
Set the low target's regmap field as appropriately. */
#ifndef __powerpc64__
- the_low_target.regmap = ppc_regmap;
if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
+ tdesc = tdesc_powerpc_e500l;
+
+ if (!ppc_regmap_adjusted)
{
- init_registers_powerpc_e500l ();
- the_low_target.regmap = ppc_regmap_e500;
- }
+ if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
+ ppc_usrregs_info.regmap = ppc_regmap_e500;

- /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
- slot and not just its second word. The PT_FPSCR supplied in a
- 32-bit GDB compilation doesn't reflect this. */
- if (register_size (70) == 8)
- ppc_regmap[70] = (48 + 2*32) * sizeof (long);
+ /* If the FPSCR is 64-bit wide, we need to fetch the whole
+ 64-bit slot and not just its second word. The PT_FPSCR
+ supplied in a 32-bit GDB compilation doesn't reflect
+ this. */
+ if (register_size (tdesc, 70) == 8)
+ ppc_regmap[70] = (48 + 2*32) * sizeof (long);
+
+ ppc_regmap_adjusted = 1;
+ }
#endif
+ current_process ()->tdesc = tdesc;
}

/* Correct in either endianness.
@@ -484,7 +520,7 @@ ppc_fill_vsxregset (struct regcache *regcache, void *buf)
if (!(ppc_hwcap & PPC_FEATURE_HAS_VSX))
return;

- base = find_regno ("vs0h");
+ base = find_regno (regcache->tdesc, "vs0h");
for (i = 0; i < 32; i++)
collect_register (regcache, base + i, &regset[i * 8]);
}
@@ -498,7 +534,7 @@ ppc_store_vsxregset (struct regcache *regcache, const void *buf)
if (!(ppc_hwcap & PPC_FEATURE_HAS_VSX))
return;

- base = find_regno ("vs0h");
+ base = find_regno (regcache->tdesc, "vs0h");
for (i = 0; i < 32; i++)
supply_register (regcache, base + i, &regset[i * 8]);
}
@@ -519,7 +555,7 @@ ppc_fill_vrregset (struct regcache *regcache, void *buf)
if (!(ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC))
return;

- base = find_regno ("vr0");
+ base = find_regno (regcache->tdesc, "vr0");
for (i = 0; i < 32; i++)
collect_register (regcache, base + i, &regset[i * 16]);

@@ -536,7 +572,7 @@ ppc_store_vrregset (struct regcache *regcache, const void *buf)
if (!(ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC))
return;

- base = find_regno ("vr0");
+ base = find_regno (regcache->tdesc, "vr0");
for (i = 0; i < 32; i++)
supply_register (regcache, base + i, &regset[i * 16]);

@@ -565,7 +601,7 @@ ppc_fill_evrregset (struct regcache *regcache, void *buf)
if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE))
return;

- ev0 = find_regno ("ev0h");
+ ev0 = find_regno (regcache->tdesc, "ev0h");
for (i = 0; i < 32; i++)
collect_register (regcache, ev0 + i, &regset->evr[i]);

@@ -582,7 +618,7 @@ ppc_store_evrregset (struct regcache *regcache, const void *buf)
if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE))
return;

- ev0 = find_regno ("ev0h");
+ ev0 = find_regno (regcache->tdesc, "ev0h");
for (i = 0; i < 32; i++)
supply_register (regcache, ev0 + i, &regset->evr[i]);

@@ -590,7 +626,7 @@ ppc_store_evrregset (struct regcache *regcache, const void *buf)
supply_register_by_name (regcache, "spefscr", &regset->spefscr);
}

-struct regset_info target_regsets[] = {
+static struct regset_info ppc_regsets[] = {
/* List the extra register sets before GENERAL_REGS. That way we will
fetch them every time, but still fall back to PTRACE_PEEKUSER for the
general registers. Some kernels support these, but not the newer
@@ -605,11 +641,35 @@ struct regset_info target_regsets[] = {
{ 0, 0, 0, -1, -1, NULL, NULL }
};

+static struct usrregs_info ppc_usrregs_info =
+ {
+ ppc_num_regs,
+ ppc_regmap,
+ };
+
+static struct regsets_info ppc_regsets_info =
+ {
+ ppc_regsets, /* regsets */
+ 0, /* num_regsets */
+ NULL, /* disabled_regsets */
+ };
+
+static struct regs_info regs_info =
+ {
+ NULL, /* regset_bitmap */
+ &ppc_usrregs_info,
+ &ppc_regsets_info
+ };
+
+static const struct regs_info *
+ppc_regs_info (void)
+{
+ return &regs_info;
+}
+
struct linux_target_ops the_low_target = {
ppc_arch_setup,
- ppc_num_regs,
- ppc_regmap,
- NULL,
+ ppc_regs_info,
ppc_cannot_fetch_register,
ppc_cannot_store_register,
NULL, /* fetch_register */
@@ -627,3 +687,27 @@ struct linux_target_ops the_low_target = {
ppc_collect_ptrace_register,
ppc_supply_ptrace_register,
};
+
+void
+initialize_low_arch (void)
+{
+ /* Initialize the Linux target descriptions. */
+
+ init_registers_powerpc_32l ();
+ init_registers_powerpc_altivec32l ();
+ init_registers_powerpc_cell32l ();
+ init_registers_powerpc_vsx32l ();
+ init_registers_powerpc_isa205_32l ();
+ init_registers_powerpc_isa205_altivec32l ();
+ init_registers_powerpc_isa205_vsx32l ();
+ init_registers_powerpc_e500l ();
+ init_registers_powerpc_64l ();
+ init_registers_powerpc_altivec64l ();
+ init_registers_powerpc_cell64l ();
+ init_registers_powerpc_vsx64l ();
+ init_registers_powerpc_isa205_64l ();
+ init_registers_powerpc_isa205_altivec64l ();
+ init_registers_powerpc_isa205_vsx64l ();
+
+ initialize_regsets_info (&ppc_regsets_info);
+}