From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 21129 invoked by alias); 15 May 2013 12:39:10 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 21116 invoked by uid 89); 15 May 2013 12:39:10 -0000 X-Spam-SWARE-Status: No, score=-8.0 required=5.0 tests=AWL,BAYES_00,KHOP_THREADED,RCVD_IN_HOSTKARMA_W,RCVD_IN_HOSTKARMA_WL,RP_MATCHES_RCVD,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.1 Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Wed, 15 May 2013 12:39:09 +0000 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id r4FCd72m028781 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Wed, 15 May 2013 08:39:07 -0400 Received: from [127.0.0.1] (ovpn01.gateway.prod.ext.ams2.redhat.com [10.39.146.11]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id r4FCd5ur015473; Wed, 15 May 2013 08:39:06 -0400 Message-ID: <519381E9.3020007@redhat.com> Date: Wed, 15 May 2013 12:39:00 -0000 From: Pedro Alves User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130311 Thunderbird/17.0.4 MIME-Version: 1.0 To: Eli Zaretskii CC: gdb-patches@sourceware.org Subject: Re: [PATCH 3/5] range stepping: gdb References: <20130514191026.13213.39574.stgit@brno.lan> <20130514191047.13213.8476.stgit@brno.lan> <83k3n173ao.fsf@gnu.org> <5193621C.50603@redhat.com> <83ppws5w00.fsf@gnu.org> In-Reply-To: <83ppws5w00.fsf@gnu.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-SW-Source: 2013-05/txt/msg00521.txt.bz2 On 05/15/2013 12:21 PM, Eli Zaretskii wrote: >> Date: Wed, 15 May 2013 11:23:24 +0100 >> From: Pedro Alves >> CC: gdb-patches@sourceware.org >> >>>> +@var{end} is the address of the first instruction beyond the step >>>> +range, and @strong{not} the address of the last instruction within it. >>>> +(This has the property that @var{start} == @var{end} single-steps >>>> +once, and only once, even if the instruction at @var{start} jumps to >>>> +@var{end}.) >>> >>> This sentence in parentheses got me completely confused. Before >>> reading it, I thought I understood what is this about; now I don't. >>> In particular, if START is equal to END, then how in the world could >>> the instruction at START jump to END? >> >> Sorry, I had that typo in the gdbserver code as well, fixed it >> there, but missed this one. >> >> It should read, even if the instruction at @var{start} jumps to @var{start}. >> >> vCont;r first steps, then checks. IOW: >> >> vCont ;r ADDR1,ADDR1 >> >> is equivalent to (and could be thought to supersede): >> >> vCont ;s >> >>> And if END is excluded from the >>> range, then why when START equals END do we step at all? Please >>> explain. >> >> It's just a design decision. I recall at least one target I saw I worked >> with that supported range stepping, and it didn't even a distinction >> between range vs no-range step commands. The way to do a single step >> was to pass both addresses the same. I find it a better design than >> requiring the target do one current-address check _before_ stepping, >> and another _after_ single-stepping. > > Doesn't this mean that these two use cases are explicit exceptions > from the rule that END is excluded? Nope. There's no exception. With: vCont ;r START,END #1 - The stub single-steps the thread. #2 - Once the thread stops, the stub checks whether the thread stopped in the [START,END) range. If so, goto #1. It not, goto #3. #3 - The stub reports to gdb that the thread stopped stepping. If it happens that START and END are the same, then #2 always goes to #3. When I said: "(This has the property that @var{start} == @var{end} single-steps once, and only once, even if the instruction at @var{start} jumps to @var{start}.)" I was trying to clarify the case of the instruction at START being: jump START Then, vCont ;r START,START always single-steps once, and only once, instead of continuously single-stepping that instruction without reporting to GDB. > If so, we should describe them as > exceptions, not use them as evidence for the rule (which they > evidently violate). > > Or did I misunderstand again? -- Pedro Alves